Side tables annotating an instruction stream
First Claim
1. A microprocessor chip, comprising:
- instruction pipeline circuitry; and
table lookup circuitry designed to retrieve an entry from a table, each entry of the table being associated with a corresponding address range translated by address translation circuitry of the microprocessor chip, each entry describing a likelihood of the existence of an alternate coding of instructions located in the respective corresponding address range, the table lookup circuitry operable as part of the basic instruction cycle of executing an instruction of a non-supervisor mode program executing on a computer;
interrupt circuitry cooperatively designed with the instruction pipeline circuitry to synchronously trigger an interrupt in accordance with interrupt criteria on execution of an instruction of a process, wherein the architectural definition of the instruction does not call for an interrupt, the interrupt criteria being based at least in part on the table entry associated with the address of the instruction, the interrupt circuitry being designed to invoke a handler for the interrupt, the handler being responsive to a content of the table entry to affect the instruction pipeline circuitry to effect control of an architecturally-visible data manipulation behavior or control transfer behavior of the instruction based on the contents of a table entry associated with the address range in which the instruction lies.
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Accused Products
Abstract
A microprocessor chip, and methods for use in that microprocessor chip. The chip has instruction pipeline circuitry and address translation circuitry. Table lookup circuitry indexes into a table, the table having an entry associated with each corresponding address range translated by the address translation circuitry. Each entry of the table describes a likelihood of the existence of an alternate coding of instructions located in the respective corresponding address range. The table lookup circuitry retrieves a table entry corresponding to the address, and is operable as part of the basic instruction cycle of executing an instruction of a non-supervisor mode program executing on a computer. Interrupt circuitry is cooperatively designed with the instruction pipeline circuitry to trigger an interrupt on execution of an instruction of a process, synchronously based at least in part on a memory state of the computer and the address of the instruction, the architectural definition of the instruction not calling for an interrupt. A handler for the interrupt is responsive to the contents of the table to affect the instruction pipeline circuitry to effect control of an architecturally-visible data manipulation behavior or control transfer behavior of the instruction based on the contents of a table entry associated with the instruction.
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Citations
77 Claims
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1. A microprocessor chip, comprising:
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instruction pipeline circuitry; and
table lookup circuitry designed to retrieve an entry from a table, each entry of the table being associated with a corresponding address range translated by address translation circuitry of the microprocessor chip, each entry describing a likelihood of the existence of an alternate coding of instructions located in the respective corresponding address range, the table lookup circuitry operable as part of the basic instruction cycle of executing an instruction of a non-supervisor mode program executing on a computer;
interrupt circuitry cooperatively designed with the instruction pipeline circuitry to synchronously trigger an interrupt in accordance with interrupt criteria on execution of an instruction of a process, wherein the architectural definition of the instruction does not call for an interrupt, the interrupt criteria being based at least in part on the table entry associated with the address of the instruction, the interrupt circuitry being designed to invoke a handler for the interrupt, the handler being responsive to a content of the table entry to affect the instruction pipeline circuitry to effect control of an architecturally-visible data manipulation behavior or control transfer behavior of the instruction based on the contents of a table entry associated with the address range in which the instruction lies.
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2. A method, comprising the steps of:
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as part of the basic instruction cycle of executing an instruction of a non-supervisor mode program executing on a computer, consulting a table, the table having entries that are indexed by the address within an address space of instructions executed, entries of the table containing attributes of instructions whose addresses index to the respective table entries; and
controlling an architecturally-visible data manipulation behavior or control transfer behavior of the instruction based at least in part on a content of a table entry indexed by the address of the instruction. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A microprocessor chip, comprising:
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instruction pipeline circuitry;
table lookup circuitry designed to index into a table by a memory address of a memory reference arising during execution of an architecturally-defined instruction, and to retrieve a table entry corresponding to the address, the table entry being distinct from the memory referenced by the memory reference;
the instruction pipeline circuitry being responsive to the contents of the table entry to alter a manipulation of data or control transfer behavior of the instruction in a manner incompatible with the architectural definition of the instruction in the instruction'"'"'s native architecture. - View Dependent Claims (15, 16, 17)
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18. A microprocessor chip, comprising:
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instruction pipeline circuitry;
address translation circuitry; and
a lookup structure having entries associated with corresponding address ranges generated by the instruction pipeline circuitry and translated by the address translation circuitry, the entries describing a likelihood of the existence of an alternate coding of instructions located in the respective corresponding address range. - View Dependent Claims (19, 20, 21, 22)
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23. A microprocessor chip, comprising:
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instruction pipeline circuitry; and
interrupt circuitry cooperatively designed with the instruction pipeline circuitry to trigger a synchronous interrupt on execution of an instruction of a process based at least in part on a memory state of the computer and the address of the instruction, wherein the architectural definition of the instruction in the instruction'"'"'s native architecture does not call for an interrupt. - View Dependent Claims (24, 25, 26, 27, 28, 29)
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30. A method, comprising the steps of:
as an integral part of processing an instruction in instruction pipeline circuitry of a computer, consulting a lookup structure of entries, entries of the lookup structure corresponding to address ranges translated by address translation circuitry, and the entries describe a likelihood of the existence of an alternate coding of instructions located in the respective corresponding address ranges. - View Dependent Claims (31, 32, 33, 34, 35, 36)
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37. A method, comprising the steps of:
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as an integral part of processing an instruction in instruction pipeline circuitry of a computer, consulting a lookup structure of entries, each entry corresponding to an address range translated by address translation circuitry, and describing a likelihood of the existence of an alternate coding of instructions located in the respective corresponding address range; and
as a result of the consulting, changing an instruction set architecture under which instructions are interpreted by the computer.
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38. A method, comprising the steps of:
on execution of an instruction of a process in a computer, triggering a synchronous interrupt based at least in part on a memory state of the computer and the address of the instruction, wherein the architectural definition of the instruction in the instruction'"'"'s native architecture does not call for an interrupt. - View Dependent Claims (39, 40, 41, 42)
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43. A method, comprising the steps of:
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as part of the basic instruction cycle of executing an architecturally-defined instruction of a non-supervisor mode program executing on a computer, retrieving an entry from a table, the table entry being indexed by the address of a memory reference arising during execution of the architecturally-defined instruction, the table entry being distinct from the memory referenced by the memory reference;
based at least in part on a content of the table entry, altering a manipulation of data or control transfer behavior of the architecturally-defined instruction in a manner incompatible with the architectural definition of the architecturally-defined instruction in the architecturally-defined instruction'"'"'s native architecture. - View Dependent Claims (44, 45, 46, 47, 48, 49, 50, 51, 52)
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53. An apparatus, comprising:
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instruction pipeline circuitry; and
table lookup circuitry designed to retrieve a table entry from a table whose entries are indexed by an address within an address space of an instruction fetched for execution by the instruction pipeline circuitry;
the instruction pipeline circuitry being responsive to a content of the table entry to control an architecturally-visible data manipulation behavior or control transfer behavior of the fetched instruction based at least in part on a content of the table entry indexed by the address of the instruction. - View Dependent Claims (54, 55, 56, 57, 58, 59)
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60. A method, comprising the steps of:
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as part of the basic instruction cycle of executing an instruction of a non-supervisor mode program fetched for execution on a computer, consulting a table, entries of the table being indexed by addresses of instructions fetched, entries of the table containing attribute indicia of instructions whose addresses index to the respective entries; and
controlling an architecturally-visible data manipulation behavior or control transfer behavior of the fetched instruction based at least in part on a content of a table entry indexed by the address of the fetched instruction, the table entries being architecturally-invisible in the fetched instruction'"'"'s native architecture. - View Dependent Claims (61, 62, 63, 64, 65, 66, 67, 68)
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69. An apparatus, comprising:
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instruction pipeline circuitry; and
table lookup circuitry designed to retrieve a table entry from a table whose entries are indexed by an address of an instruction fetched for execution, the table being stored in storage that is architecturally invisible to programs in the fetched instruction'"'"'s native architecture;
the instruction pipeline circuitry being responsive to a content of the table entry to control an architecturally-visible data manipulation behavior or control transfer behavior of the fetched instruction based at least in part on a content of the table entry associated with the address of the fetched instruction. - View Dependent Claims (70, 71, 72, 73, 74, 75, 76)
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77. A microprocessor chip, comprising:
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instruction pipeline circuitry; and
table lookup circuitry designed to retrieve an entry from a table, each entry of the table being associated with a corresponding address range of an address space translated by address translation circuitry of the microprocessor chip, each entry describing a likelihood of the existence of an alternate coding of instructions located in the respective corresponding address range, the table lookup circuitry operable as part of the basic instruction cycle of executing an instruction of a non-supervisor mode program for execution on the microprocessor chip, the table being stored in storage that is architecturally invisible to programs in the native architecture of at least some instructions executed by the microprocessor chip;
interrupt circuitry cooperatively designed with the instruction pipeline circuitry to trigger a synchronous interrupt on execution of an instruction of a process, wherein the architectural definition of the instruction of the process does not call for an interrupt, a trigger for the interrupt being synchronously based at least in part on the table entry corresponding to the address of the instruction of the process, the interrupt circuitry being designed to invoke a handler for the interrupt, the handler being responsive to a content of the table entry to affect the instruction pipeline circuitry to effect control of an architecturally-visible data manipulation behavior or control transfer behavior of the instruction of the process, based at least in part on the contents of a table entry corresponding to the address range in which the instruction of the process lies.
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Specification