System and method for execution of a secured environment initialization instruction
First Claim
Patent Images
1. A system, comprising:
- a first logical processor including a secure memory to execute a secured enter instruction; and
a chipset to prevent access to a secured virtual machine monitor by a non-processor device.
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Accused Products
Abstract
A method and apparatus for initiating secure operations in a microprocessor system is described. In one embodiment, one initiating logical processor initiates the process by halting the execution of the other logical processors, and then loading initialization and secure virtual machine monitor software into memory. The initiating processor then loads the initialization software into secure memory for authentication and execution. The initialization software then authenticates and registers the secure virtual machine monitor software prior to secure system operations.
277 Citations
49 Claims
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1. A system, comprising:
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a first logical processor including a secure memory to execute a secured enter instruction; and
a chipset to prevent access to a secured virtual machine monitor by a non-processor device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method, comprising:
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synchronizing a first logical processor and a second logical processor;
authenticating an initialization code module;
authenticating a secure virtual machine monitor; and
executing said secure virtual machine monitor. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. An apparatus, comprising
means for synchronizing a first logical processor and a second logical processor; -
means for authenticating an initialization code module;
means for authenticating a secure virtual machine monitor; and
means for execution of said secure virtual machine monitor in said first logical processor. - View Dependent Claims (19, 20, 21, 22)
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23. A processor, comprising:
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secure enter logic to execute a first instruction to invoke secure operation initialization, and to detect a point in time to proceed with execution of a secure initialization authenticated code; and
bus messaging logic to send a first special bus message responsive to said first instruction, and to send a second special bus message responsive to said detected point in time. - View Dependent Claims (24, 25, 26, 27)
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28. A chipset, comprising:
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a bus messaging logic responsive to a first special bus message from a first logical processor to prepare for secure operation; and
a register to store an acknowledgement from a second logical processor responsive to said first special bus message. - View Dependent Claims (29, 30, 31, 32)
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33. A system, comprising:
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a logical processor having a secure enter logic, and a first bus messaging logic responsive to said secure enter logic; and
a chipset having a second bus messaging logic to receive a first special bus message from said first bus messaging logic, and a flag to set responsive to an acknowledgement. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40, 41)
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42. A method, comprising:
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transmitting a special bus message;
authenticating an initialization code within a first logical processor;
authenticating a secure virtual machine monitor; and
executing said secure virtual machine monitor in said first logical processor. - View Dependent Claims (43, 44, 45, 46, 47, 48, 49)
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Specification