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Inter-procedure global register allocation method

  • US 7,069,548 B2
  • Filed: 06/28/2002
  • Issued: 06/27/2006
  • Est. Priority Date: 06/28/2002
  • Status: Expired due to Fees
First Claim
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1. A method for optimizing processor register allocation, comprising:

  • identifying a plurality of variables from an acyclic call graph having a plurality of functions;

    creating a plurality of virtual registers by assigning each of the plurality of variables to at least one virtual register;

    constructing an interference graph based on the plurality of virtual registers, wherein constructing the interference graph includes sorting the acyclic call graph into a doubly-linked list;

    coloring the interference graph with a plurality of physical registers; and

    if the interference graph is not colorable, spilling at least one virtual register from the interference graph.

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