System time clock capture for computer satellite receiver

• US 7,069,574 B1
• Filed: 08/29/2000
• Issued: 06/27/2006
• Est. Priority Date: 09/02/1999
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadlogic Network Technologies, Inc. (Broadcom, Inc.)
• Inventors: Fuller, Randy R, Adams, Thomas G
• Primary Examiner(s): VU, NGOC K
• Application Number:
  US09/650,329
• Time in Patent Office: 2,128 Days
• Field of Search: 348/500, 348/464, 348/469, 348/516, 348/518, 348/521, 725/68, 725131-132, 725139-140, 725151-152, 370/468, 370/503, 370/509, 370/512, 370/517, 370/519
• US Class Current: 725/68
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/6143 involving transmission via a satellite
• CPC Class Codes: H04N 7/20 Adaptations for transmission via a GHz frequency band, e.g. via satellite

Abstract

A method and system are provided for synchronizing a digital video system that includes a transmitter, a receiver, and a decoder. A transport packet is received from the transmitter. At the start of receiving the transport packet, a system time clock timestamp is captured. A program clock reference timestamp is also obtained from the transport packet and is compared with the system time clock timestamp.

Claims

1. A method for synchronizing a system including a host computer having a microprocessor, a receiver circuit and a decoder circuit, the method comprising:

(a) coupling the receiver circuit with the decoder circuit and the microprocessor, wherein the receiver circuit, decoder circuit, and microprocessor each comprise separate nodes of a bus in the host computer;

(b) maintaining synchronization between the receiver circuit and a transmitter external to the host computer by receiving a first transport packet from the transmitter with the receiver circuit;

capturing a first system time clock (STC) timestamp at a start of receiving the first transport packet, the first STC timestamp being captured into a latch in the receiver circuit;

obtaining a program clock reference (PCR) timestamp from the transport packet;

comparing the first STC timestamp to the PCR timestamp to generate a comparison result; and

adjusting a STC frequency based on the comparison result by using firmware within the receiver circuit;

(c) capturing, with the decoder circuit, a second STC timestamp; and

(d) adjusting a system timestamp with an offset based on a message delay time between the second STC timestamp and a last PCR timestamp received maintain synchronization between the decoder circuit and the receiver circuit.

2. The method according to claim 1 wherein the decoder circuit comprises an audio-visual interface.

3. The method according to claim 1 wherein the decoder circuit comprises a computer network interface.

4. The method according to claim 1 wherein the offset is scaled by a nonunity value.

5. A system for synchronizing a system including a host computer having a microprocessor, a receiver circuit and a decoder circuit, the system comprising:

(a) a bus in the host computer having the microprocessor, the receiver circuit and the decoder circuit on separate nodes thereof;

(b) the receiver circuit being adapted to maintain the synchronization between the receiver circuit and a transmitter external to the host computer, the receiver circuit comprising;

a parser adapted to obtain a program clock reference (PCR) timestamp from a first transport packet, the first transport packet including the PCR timestamp;

a first latch coupled to the parser, the first latch being adapted to capture a first system time clock (STC) timestamp near a beginning of receipt of a first transport packet from a transmitter by the receiver circuit;

a comparison device coupled to the parser and to the latch, the comparison device being configured to compare the first STC timestamp to the PCR timestamp so as to generate a comparison result; and

a first adjuster coupled to the comparison device, the first adjuster being adapted to adjust a frequency of the system time clock based on the comparison result by using firmware within the receiver circuit;

(c) the decoder circuit configured to capture a second STC timestamp; and

(d) wherein the system adjusts a system timestamp with an offset based on a message delay time between the second STC timestamp and a last PCR timestamp received.

6. The system according to claim 5 wherein the decoder circuit comprises an audio-visual interface.

7. The system according to claim 5 wherein the decoder circuit comprises a computer network interface.

8. The system according to claim 5 wherein the offset is scaled by a nonunity value.

9. A method for synchronizing a system including a host computer having a microprocessor, a receiver circuit and a decoder circuit, the method comprising:

(a) coupling the receiver circuit with the decoder circuit and the microprocessor, where the receiver circuit decoder circuit, and microprocessor each comprise separate nodes of a bus in the host computer;

(b) maintaining synchronization between the receiver circuit and a transmitter external to the host computer by receiving a first transport packet from the transmitter with the receiver circuit;

capturing a first system time clock (STC) timestamp at a start of receiving the first transport packet, the first STC timestamp being captured into a latch in the receiver circuit;

obtaining a program clock reference (PCR) timestamp from the transport packet;

comparing the first STC timestamp to the PCR timestamp to generate a comparison result; and

adjusting a STC frequency based on the comparison result by using firmware within the receiver circuit;

(c) writing into a first register in a bus interface;

(d) latching a second STC timestamp into a second register in the bus interface wherein the writing into the first register causes the second STC timestamp to be latched into the second register; and

(e) retrieving the second STC timestamp to the decoder circuit by way of the second register.

10. The method according to claim 9 wherein the decoder circuit comprises an audio-visual interface.

11. The method according to claim 9 wherein the decoder circuit comprises a computer network interface.

12. A system for synchronizing a system including a host computer having a microprocessor, a receiver circuit and a decoder circuit, the system comprising:

(a) a bus in the host computer that couples the receiver circuit with the decoder circuit and the microprocessor, wherein the receiver circuit, the decoder circuit, and the microprocessor each comprise separate nodes of the bus;

(b) the receiver circuit being adapted to maintain the synchronization between the receiver circuit and a transmitter and external to the host computer, the receiver circuit comprising;

a parser adapted to obtain a program clock reference (PCR) timestamp from a first transport packet, the first transport packet including the PCR timestamp;

a first latch coupled to the parser, the first latch being adapted to capture a first system time clock (STC) timestamp near a beginning of receipt of a first transport packet from a transmitter by the receiver circuit;

a comparison device coupled to the parser and to the latch, the comparison device being configured to compare the first STC timestamp to the PCR timestamp so as to generate a comparison result; and

a first adjuster coupled to the comparison device, the first adjuster being adapted to adjust a frequency of the system time clock based on the comparison result by using firmware within the receiver circuit;

(c) a first register in a bus interface; and

(d) a second register in the bus interface, the second register being adapted to latch a second STC timestamp, wherein writing into the first register causes the second STC timestamp to latched into the second register wherein the second STC timestamp is provided to the decoder circuit by way of the second register.

13. The system according to claim 12 wherein the decoder circuit comprises an audio-visual interface.

14. The system according to claim 12 wherein the decoder circuit comprises a computer network interface.