BARC shaping for improved fabrication of dual damascene integrated circuit features

• US 7,071,112 B2
• Filed: 10/21/2002
• Issued: 07/04/2006
• Est. Priority Date: 10/21/2002
• Status: Expired due to Fees

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Leung, Terry, Zhang, QiQun, Halim, Silvia, Yuan, Jie, Hsieh, Chang-Lin
• Primary Examiner(s): CHEN, KIN CHAN
• Application Number:
  US10/278,233
• Publication Number:
  US 20040077175A1
• Time in Patent Office: 1,352 Days
• Field of Search: 438/700, 438/706, 438/710, 438/714, 438/723, 438/724, 438/725
• US Class Current: 438/700
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material

Abstract

Method, materials and structures are described for the fabrication of dual damascene features in integrated circuits. In via-first dual damascene fabrication, a bottom-antireflective-coating (“BARC”) is commonly deposited into the via and field regions surrounding the via, 107. Subsequent trench etch with conventional etching chemistries typically results in isolated regions of BARC, 107a, surrounded by “fencing” material, 108, at the bottom of the via. Such fencing hinders conformal coating with barrier/adhesion layers and can reduce device yield. The present invention relates to the formation of a BARC plug, 107c, partially filling the via and having a convex upper surface, 400, prior to etching the trench. Such a BARC structure is shown to lead to etching without the formation of fencing and a clean dual damascene structure for subsequent coating. A directional, anisotropic etching of BARC, and more particularly, an ammonia plasma etch, is one convenient method of removing BARC and forming the desired convex upper surface.

Claims

1. A method of forming a dual damascene structure during the fabrication of an integrated circuit comprising:

a) forming a via through at least one insulator layer;

b) depositing a bottom-antireflective-coating material into said via and onto the field regions adjacent said via;

c) depositing a photoresist on said bottom-antireflective-coating material;

d) patterning said photoresist above said via in the form of a trench, exposing thereby one or more regions of said bottom-antireflective-coating material;

e) directionally etching said bottom-antireflective-coating material to a level partially filling said via and such that the upper surface of said bottom-antireflective-coating material is convex; and

f) etching a trench through said at least one insulator layer to a depth less than the depth of said via.

2. A method as in claim 1 wherein said at least one insulator layer comprises at least one oxide layer.

3. A method as in claim 1 wherein said directional etch is by ammonia plasma.

4. A method as in claim 3 wherein said ammonia plasma has a flow rate in the range from approximately 20 standard cubic feet per minute to approximately 500 standard cubic feet per minute.

5. A method as in claim 4 wherein said ammonia plasma has a flow rate of approximately 175 standard cubic feet per minute.

6. A method as in claim 3 wherein said ammonia plasma has a pressure in the range from approximately 20 milliTorr to approximately 300 milliTorr.

7. A method as in claim 6 wherein said ammonia plasma has a pressure of approximately 100 milliTorr.

8. A method as in claim 3 wherein said ammonia plasma has electrical power in the range from approximately 200 watts to approximately 1000 watts.

9. A method as in claim 8 wherein said ammonia plasma has electrical power of approximately 600 watts.

10. A method as in claim 1 further comprising:

g) stripping said photoresist and said bottom-antireflective-coating material; and

h) depositing a coating layer substantially conformally on the interior surfaces of said trench and said via.

11. A method as in claim 10 wherein said coating layer is a barrier/adhesion layer.

12. A method as in claim 11 further comprising:

i) depositing an electrical conductor on said coating layer.

13. A method as in claim 12 wherein said electrical conductor is copper.

14. A method of reducing fencing in the formation of a dual damascene integrated circuit structure comprising:

a) forming a via through at least one insulator layer;

b) depositing a bottom-antireflective-coating material into said via and onto the field regions adjacent said via;

c) depositing a photoresist on said bottom-antireflective-coating material;

d) patterning said photoresist above said via in the form of a trench, exposing thereby one or more regions of said bottom-antireflective-coating material;

e) directionally etching said bottom-antireflective-coating material to a level partially filling said via and such that the upper surface of said bottom-antireflective-coating material is convex; and

f) etching a trench through said at least one insulator layer to a depth less than the depth of said via.

15. A method as in claim 14 wherein said at least one insulator layer comprises at least one oxide layer.

16. A method as in claim 14 wherein said directional etch is by ammonia plasma.

17. A method as in claim 16 wherein said ammonia plasma has a flow rate in the range from approximately 20 standard cubic feet per minute to approximately 500 standard cubic feet per minute.

18. A method as in claim 17 wherein said ammonia plasma has a flow rate of approximately 175 standard cubic feet per minute.

19. A method as in claim 16 wherein said ammonia plasma has a pressure in the range from approximately 20 milliTorr to approximately 300 milliTorr.

20. A method as in claim 19 wherein said ammonia plasma has a pressure of approximately 100 milliTorr.

21. A method as in claim 16 wherein said ammonia plasma has electrical power in the range from approximately 200 watts to approximately 1000 watts.

22. A method as in claim 21 wherein said ammonia plasma has electrical power of approximately 600 watts.

23. A method as in claim 14 further comprising:

g) stripping said photoresist and said bottom-antireflective-coating material; and

h) depositing a coating layer substantially conformally on the interior surfaces of said trench and said via.

24. A method as in claim 23 wherein said coating layer is a barrier/adhesion layer.

25. A method as in claim 24 further comprising:

i) depositing an electrical conductor on said coating layer.

26. A method as in claim 25 wherein said electrical conductor is copper.