Wafer-level package having test terminal

• US 7,071,487 B2
• Filed: 05/12/2004
• Issued: 07/04/2006
• Est. Priority Date: 12/28/1998
• Status: Expired due to Fees

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Maruyama, Shigeyuki
• Primary Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US10/843,301
• Publication Number:
  US 20040206954A1
• Time in Patent Office: 783 Days
• Field of Search: 257/48, 257/620, 257/784, 257/786, 257/698, 257/696, 257/211, 257/208, 257/203, 257/207, 324/765, 324/73.1, 324/537, 324/158.R
• US Class Current: 257/48
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24195 the item being a discrete passive component
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

A wafer-level package includes a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit each provided with test chip terminals and non test chip terminals, at least one external connection terminal, at least one redistribution trace provided on the semiconductor wafer, at least one testing member, and an insulating material. A first end of the redistribution trace is connected to one of the test chip terminals and a second end of said redistribution trace is extended out to a position offset from the chip terminals. The testing member is provided in an outer region of the semiconductor chip circuit forming region, and the second end of the redistribution trace is connected to the testing member.

Claims

1. A wafer-level package comprising:

a semiconductor wafer having at least one semiconductor chip circuit forming region that includes a semiconductor chip circuit and a plurality of chip terminals, said chip terminals including at least one test chip terminal and at least one non-test chip terminal;

at least one external connection terminal electrically connected to said at least one non-test chip terminal;

at least one redistribution trace provided on said semiconductor wafer, a first end of said redistribution trace being electrically connected to said at least one test chip terminal and a second end of said redistribution trace being extended out to a position offset from one of said chip terminals;

at least one test terminal, exclusively for testing, provided in an outer region outside said semiconductor chip circuit forming region, said second end of said redistribution trace being electrically connected to said at least one test-terminal; and

an insulating material covering at least said redistribution trace, said at least one external connection terminal and said at least one test terminal being exposed from said insulating material,

wherein said at least one test terminal is provided in said outer region and corresponds to said at least one semiconductor chip circuit forming region.

4. The wafer-level package as claimed in claim 1, wherein said outer region forms a dicing area.

5. The wafer-level package as claimed in claim 1, wherein said at least one external connection terminal is provided within said semiconductor chip circuit forming region.

2. A wafer-level package comprising:

a semiconductor wafer having a plurality of semiconductor chip circuit forming regions each including a semiconductor chip circuit and a plurality of chip terminals, said chip terminals including at least one test chip terminal and at least one non-test chip terminal;

at least one external connection terminal electrically connected to said at least one non-test chip terminal;

at least one redistribution trace provided on said semiconductor wafer, a first end of said redistribution trace being electrically connected to said at least one test chip terminal and a second end of said redistribution trace being extended out to a position offset from one of said chip terminals;

a plurality of test terminals, exclusively for testing, provided in an outer region outside said semiconductor chip circuit forming region, said second end of said redistribution trace being electrically connected to at least one of the test terminals;

a common line electrically connecting at least two of the test terminals; and

an insulating material covering at least said redistribution trace, said at least one external connection terminal and said test terminals being exposed from said insulating material,

wherein said test terminals corresponding to a plurality of said semiconductor chip circuit forming regions, said test terminals and said common line being provided in said outer region.

6. The wafer-level package as claimed in claim 2, wherein said outer region forms a dicing area.

7. The wafer-level package as claimed in claim 2, wherein said at least one external connection terminal is provided within said semiconductor chip circuit forming region.

3. A wafer-level semiconductor device comprising:

a semiconductor wafer having chip circuit forming regions, each of said chip circuit forming regions having at least one test chip terminal provided therein;

at least one test terminal provided in an outer region outside the chip circuit forming regions; and

at least one redistribution line electrically connecting said at least one test terminal and said at least one test chip terminal.

8. The wafer-level semiconductor device as claimed in claim 3, wherein said outer region forms a dicing area.

9. The wafer-level semiconductor device as claimed in claim 3, wherein each of said chip circuit forming regions has at least one non-test chip terminal provided therein, and at least one external connection terminal electrically connected to said at least one non-test chip terminal.