Space-saving packaging of electronic circuits

• US 7,071,546 B2
• Filed: 03/12/2003
• Issued: 07/04/2006
• Est. Priority Date: 01/16/2002
• Status: Active Grant

• Current Assignee: Alfred E. Mann Foundation For Scientific Research
• Original Assignee: Alfred E. Mann Foundation For Scientific Research
• Inventors: Fey, Kate E., Mandell, Lee J., Byers, Charles L.
• Primary Examiner(s): Wilczewski, Mary
• Assistant Examiner(s): Lewis, Monica
• Application Number:
  US10/345,013
• Publication Number:
  US 20030192171A1
• Time in Patent Office: 1,210 Days
• Field of Search: 257/678, 257/685, 257/686, 257/787, 257/698, 257/777
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: Y10T 29/53104 Roller or ball bearing

Abstract

An apparatus and packaging method for stacking a plurality of integrated circuit substrates, i.e., substrates having integrated circuits formed as integral portions of the substrates, which provides interconnection paths through the substrates to simplify electrical connections between the integrated circuits while facilitating minimization of the volume and customization of the three dimensional package size to conform to the available internal space within a housing, e.g., one used in an implantabie device where package volume is at a premium. Furthermore, an internal cavity can be created by the stacked formation that is suitable for mounting of a surface mount device, e.g., a crystal or the like.

Claims

1. A chip stack for forming a circuit of a plurality of integrated circuits formed on discrete semiconductor substrates, said chip stack comprising:

a first semiconductor substrate having first and second faces and an integrally formed first integrated circuit having one or more interconnection pads formed proximate to said first face of said first semiconductor substrate, wherein said first semiconductor substrate additionally comprises a plurality of electrical interconnection pathways selected from the set of electrically conductive vias that pass directly through from said first face to said second face of said first semiconductor substrate, electrically conductive vias that pass internally in a step-wise manner from said first face to said second face of said first semiconductor substrate, and electrically conductive vias that pass from one or more of said first integrated circuit interconnection pads to pads at said second surface of said first semiconductor substrate;

a second semiconductor substrate having first and second faces and an integrally formed second integrated circuit having one or more interconnection pads formed proximate to said first face of said second semiconductor substrate, wherein said second semiconductor substrate additionally comprises a plurality of electrical interconnection pathways selected from the set of electrically conductive vias that pass directly through from said first face to said second face of said second semiconductor substrate, electrically conductive vias that pass internally in a step-wise manner from said first face to said second face of said second semiconductor substrate, and electrically conductive vias that pass from one or more of said second integrated circuit interconnection pads to pads at said second surface of said second semiconductor substrate;

one or more of said interconnection pathways from said first semiconductor substrate to said second semiconductor substrate enable electrical interconnections between said first integrated circuit to said second integrated circuit when said first and second semiconductor substrates are vertically stacked; and

wherein

at least one of said interconnection pathways is comprised of an electrically conductive via that passes internally through at least one of said semiconductor substrates in a step-wise manner.

2. The chip stack of claim 1 wherein said stack of semiconductor substrates are encapsulated with a coating to hermetically seal said integrated circuits contained within.

3. The chip stack of claim 2 wherein said encapsulation is alumina.

4. The chip stack of claim 2 wherein said hermetically sealed stack is suitable for implantation in a patient'"'"'s body.

5. The chip stack of claim 1 additionally comprising:

a third semiconductor substrate having first and second faces and an integrally formed third integrated circuit having one or more interconnection pads formed proximate to said first face of said third semiconductor substrate, wherein said third semiconductor substrate additionally comprises a plurality of electrical interconnection pathways selected from the set of electrically conductive vias that pass directly through from said first face to said second face of said third semiconductor substrate, electrically conductive vias that pass in a step-wise manner from said first face to said second face of said third semiconductor substrate, and electrically conductive vias that pass from one or more of said third integrated circuit interconnection pads to pads at the third surface of said third semiconductor substrate; and

wherein

one or more of said interconnection pathways from said third semiconductor substrate to said second semiconductor substrate enable electrical interconnections between said third integrated circuit to integrated circuits selected from the set of said first and said second integrated circuits when said first, second, and third semiconductor substrates are vertically stacked.

6. The chip stack of claim 5 wherein said stack of semiconductor substrates are encapsulated with a coating to hermetically seal said integrated circuits contained within.

7. The chip stack of claim 5 additionally comprising:

a fourth semiconductor substrate having first and second faces, wherein said fourth semiconductor substrate additionally comprises a plurality of electrical interconnection pathways selected from the set of electrically conductive vias that pass directly through from said first face to said second face of said fourth semiconductor substrate, and electrically conductive vias that pass in a step-wise manner from said first face to said second face of said fourth semiconductor substrate; and

wherein

said fourth semiconductor substrate is used within a chip stack of at least said first and said second semiconductor substrates to facilitate electrical interconnections between said first and said second integrated circuits.

8. The chip stack of claim 7 wherein said stack of semiconductor substrates are encapsulated with a coating to hermetically seal said integrated circuits contained within.

9. The chip stack of claim 1 wherein said semiconductor substrates are essentially uniform in size.

10. The chip stack of claim 1 wherein said stack is formed of a plurality of differently-sized semiconductor substrates stacked in an order to form a stacked shape having a non-rectangular cross section.

11. The chip stack of claim 10 wherein said stacked shape is configured to facilitate placement within a housing.

12. The chip stack of claim 10 wherein said stacked shape is configured to facilitate placement within an elongated housing having an axial dimension of less than 60 mm and a lateral dimension of less than 6 mm.

13. The chip stack of claim 10 wherein said stack is formed of a plurality of differently-sized semiconductor substrates stacked in order to form a stacked shape having an essentially non-rectangular cross section selected from the set of circular, semi-circular, triangular, diamond, and hexagonal cross sections.

14. The chip stack of claim 1 wherein said stack is formed of a plurality of differently-sized semiconductor substrates stacked in order to cause a cavity to be formed within the chip stack, and wherein one or more surface mount devices are mounted on a face of at least one of the semiconductor substrate within said cavity.

15. The chip stack of claim 14 wherein said surface mount devices are selected from the set of piezoelectric devices and capacitors.

16. The chip stack of claim 14 wherein at least one surface mount device comprises a crystal mounted on a face of at least one of the semiconductor substrate faces within said cavity.

17. The chip stack of claim 14 wherein said stack of semiconductor substrates are encapsulated with a coating to hermetically seal said integrated circuits contained within.