Patterning three dimensional structures

• US 7,071,565 B2
• Filed: 09/26/2002
• Issued: 07/04/2006
• Est. Priority Date: 12/22/2000
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Cleeves, James M., Subramanian, Vivek, Li, Calvin K., Knall, N. Johan, Vyvoda, Michael A.
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): MANDALA, VICTOR A
• Application Number:
  US10/255,884
• Publication Number:
  US 20030025210A1
• Time in Patent Office: 1,377 Days
• Field of Search: 257/775, 257/776, 257/734, 257/108, 257/421, 257/423, 257/427, 257/295, 257/774, 257/758, 365/175, 365/242, 365/243
• US Class Current: 257/775
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A three dimensional circuit structure including tapered pillars between first and second signal lines. An apparatus including a first plurality of spaced apart coplanar conductors disposed in a first plane over a substrate; a second plurality of spaced apart coplanar conductors disposed in a second plane, the second plane parallel to and different from the first plane; and a plurality of cells disposed between one of the first conductors and one of the second conductors, wherein each of the plurality of cells have a re-entrant profile.

Claims

1. A structure in a three dimensional circuit wherein the three dimensional circuit comprises a plurality of memory cell levels built over a substrate, the structure comprising tapered pillars between first and second signal lines.

2. The structure of claim 1, wherein each pillar comprises a base having a relatively smaller cross-section towards the substrate and a relatively larger cross-section away from the substrate.

3. The structure of claim 2, wherein each pillar has a sidewall, and the sidewall forms an angle of between about 85 and about 90 degrees relative to a plane parallel in the substrate.

4. The structure of claim 1, further comprising a first plurality of conductive signal lines in a first plane and a second plurality of conductive signal lines in a different second plane, and a portion of the pillars are coupled to and disposed between the first plurality of conductive signal lines and the second plurality of conductive signal lines.

5. The structure of claim 1, wherein more than one of the plurality of memory cell levels comprises an active device.

6. The structure of claim 1, wherein the tapered pillars comprise a memory element.

7. The structure of claim 6, wherein the tapered pillars further comprise at least one steering element.

8. The structure of claim 7, wherein the at least one steering element comprises a diode.

9. An apparatus comprising:

a first plurality of spaced apart coplanar conductors disposed in a first plane over a substrate;

a second plurality of spaced apart coplanar conductors disposed in a second plane, the second plane parallel to and different from the first plane and the substrate; and

a plurality of cells coupled to and disposed between one of the first conductors and one of the second conductors,

wherein each of the plurality of cells has a re-entrant profile, and

wherein at least one of the plurality of cells comprises an active device.

10. The apparatus of claim 9, wherein the re-entrant profile is between 85 degrees and 90 degrees relative to the first and second planes.

11. The apparatus of claim 9, wherein a portion of the plurality of cells comprises a memory element.

12. The apparatus of claim 9, wherein a portion of the plurality of cells comprises a steering element.

13. The apparatus of claim 12, wherein the steering element comprises a diode.

14. A three dimensional circuit structure comprising tapered pillars between first and second signal lines disposed in different planes over a substrate, the tapered pillars comprising at least one active device.

15. The structure of claim 14, further comprising a substrate, wherein each pillar comprises a base having a relatively smaller cross-section towards the substrate and a relatively larger cross-section away from the substrate.

16. The structure of claim 14, wherein each pillar has a sidewall, and the sidewall forms an angle of between about 85 and about 90 degrees relative to a plane parallel to the substrate.