Electrical package capable of increasing the density of bonding pads and fine circuit lines inside a interconnection

• US 7,071,569 B2
• Filed: 06/09/2004
• Issued: 07/04/2006
• Est. Priority Date: 08/14/2003
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Ho, Kwun-Yao, Kung, Moriss
• Primary Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US10/709,954
• Publication Number:
  US 20050035464A1
• Time in Patent Office: 755 Days
• Field of Search: 257/778, 257/779, 257/734, 257/738, 257/737, 257/700, 257/701, 257/712, 257/713, 257/717, 257/675, 257/696, 257690-693, 257/773, 257/774, 257/668, 257/678, 257/E23.063, 257/E23.062, 257/E23.011, 257/E23.006
• US Class Current: 257/778
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 2201/09472 Recessed pad for surface mounting recess in pad H05K2201/09745; Recessed electrode of component
• CPC Class Codes: H05K 3/3436 having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

An electrical package and manufacturing method thereof is provided. A high stiffness, high electrical conductivity, low coefficient of thermal expansion and high thermal conductivity support substrate is used as an initial layer for building the package. A multilayer interconnection structure is formed over the support substrate. Thereafter, a plurality of openings is formed over the support substrate. The openings expose a plurality of bonding pads on a bottom surface of the multi-layer interconnection structure. An electronic device is set up over the multi-layer interconnection structure. Contacts are formed inside the opening over the bonding pads.

Claims

1. An electrical package comprising:

a multi-layer interconnection structure having a top surface, a bottom surface and an inner circuit therein, wherein the inner circuit has a plurality of bonding pads on the bottom surface of the multi-layer interconnection structure;

at least an electronic device positioned on the top surface of the multi-layer interconnection structure and electrically connected to the inner circuit of the multi-layer interconnection structure;

a support substrate made from a conductive material, wherein the support substrate is positioned on the bottom surface of the multi-layer interconnection structure, and the support substrate has a plurality of first openings, each first opening exposing one of the corresponding bonding pads; and

an insulation layer covering the support substrate and exposing the bonding pads.

2. The electrical package of claim 1, further comprising a patterned barrier layer covering the bonding pads and exposed by the first openings.

3. The electrical package of claim 1, wherein the electronic device comprises a die, a passive component or an electrical package.

4. The electrical package of claim 1, wherein material constituting the support substrate comprises a metallic material or an alloy.

5. The electrical package of claim 1, wherein the package further comprises a plurality of contacts connected to various bonding pads through corresponding first openings.

6. The electrical package of claim 5, wherein the contacts are configured as solder balls, pins or electrode blocks.

7. The electrical package of claim 5, wherein at least one of the contacts completely fills the first opening so that the contact is electrically connected to the support substrate.

8. The electrical package of claim 1, wherein the insulation layer exposes a sidewall of at least one of the first openings.

9. The electrical package of claim 1, the package further comprises a solder mask layer disposed over a sidewall of at least one of the first openings.

10. The electrical package of claim 1, wherein the electronic device is electrically connected to the inner circuit within the multi-layer interconnection structure through flip-chip bonding, wire-bonding or a thermal pressure bonding.

11. The electrical package of claim 1, further comprising a patterned barrier layer and a plurality of conductive vias, the patterned barrier layer covering the bonding pads and the conductive vias disposing on the patterned barrier layer, wherein the patterned barrier layer and the conductive vias are exposed by the first openings.

12. The electrical package of claim 11, further comprises a plurality of contacts, each contact electrically connecting to one of the conductive vias and the patterned barrier layer, such that the contacts are electrically connected to the bonding pads through the patterned barrier layer and the conductive vias.