Inverting zipper repeater circuit

• US 7,071,747 B1
• Filed: 06/15/2004
• Issued: 07/04/2006
• Est. Priority Date: 06/15/2004
• Status: Expired due to Fees

• Current Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Original Assignee: Transmeta Corporation (Novafora, Inc.)
• Inventors: Masleid, Robert P.
• Primary Examiner(s): Cunningham, Terry D.
• Assistant Examiner(s): Hiltunen, Thomas J
• Application Number:
  US10/869,012
• Time in Patent Office: 749 Days
• Field of Search: 327/112, 327/170, 327/375, 327/376, 327/227
• US Class Current: 327/170
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 5/12 by steepening leading or trailing edges

Abstract

Repeater circuits including an inverting zipper repeater circuit and an inverting gain-enhanced repeater circuit are described.

Claims

1. An inverting zipper repeater circuit comprising:

a holding subcircuit coupled to receive an input signal and coupled to an output terminal;

a delay chain of inverters coupled to receive said input signal;

a first pulse generator comprising said delay chain inverters coupled to receive said input signal and for generating a rising output transition at said output terminal;

a first latching circuit coupled an output node of said first pulse generator and to said output terminal, wherein said first pulse generator further comprises;

a NOR gate with input nodes coupled to receive a signal from said delay chain of inverters and said input signal; and

an NFET coupled to an output node of said NOR gate, said NFET coupled to said first latching circuit;

a second pulse generator comprising said delay chain of inverters coupled to receive said input signal and for generating a falling output transition at said output terminal; and

a second latching circuit coupled an output node of said second pulse generator and to said output terminal.

2. The inverting zipper repeater circuit of claim 1, wherein said first pulse generator is responsive to a falling edge of said input signal.

3. The inverting zipper repeater circuit of claim 1, wherein said second pulse generator is responsive to a rising edge of said input signal.

4. The inverting zipper repeater circuit of claim 1, wherein said latching circuit comprises:

a precharge circuit coupled to said output node of said first pulse generator; and

a half latch circuit coupled to said first output node.

5. The inverting zipper repeater circuit of claim 1, wherein said second pulse generator further comprises:

a NAND gate with input nodes coupled to receive a signal from said delay chain of inverters and said input signal;

a PFET coupled to an output node of said NAND gate, said PFET coupled to said second latching circuit.

6. The inverting zipper repeater circuit of claim 5, wherein said latching circuit comprises:

a precharge circuit coupled to said output node of said second pulse generator; and

a half latch circuit coupled to said second output node.