Method for multiple-phase splitting by phase interpolation and circuit the same

• US 7,071,750 B2
• Filed: 10/08/2003
• Issued: 07/04/2006
• Est. Priority Date: 10/10/2002
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Lin, Roger
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Luu, An T.
• Application Number:
  US10/680,150
• Publication Number:
  US 20050001665A1
• Time in Patent Office: 1,000 Days
• Field of Search: 327/238, 331/57, 331/45
• US Class Current: 327/251
• CPC Class Codes: H03K 2005/00286 Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency
• CPC Class Codes: H03K 23/68 with a base which is a non-integer
• CPC Class Codes: H03K 3/0322 with differential cells
• CPC Class Codes: H03K 5/08 by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/1506 with parallel driven output stages; with synchronously driven series connected output stages
• CPC Class Codes: H03L 7/0998 using phase interpolation
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

The invention relates to a method and related circuitry for multiple phase-splitting. The method includes: while generating M output clocks with a same frequency f1 and different phases, generating N reference clocks with a same frequency (M/N)*f1 and different phases (wherein M>N), and triggering (N/M) frequency division using different periods within each reference clock to generate (M/N) output clocks of different phases for each reference clock, such that the M output clocks of different phases are generated from the N reference clocks of different phases.

Claims

1. A method of phase splitting for generating multi-phase clocks having the same frequency and predetermined phase differences between one another, comprising:

a plurality of reference clocks each generating an output of a first frequency having a first phase difference from other reference clocks;

for each of the plurality of reference clocks, utilizing a plurality of periods in the output of a single reference clock to generate a plurality of output clocks each having a second frequency at a second phase difference from other output clocks generated by said single reference clock, each period of the second frequency being equal to the sum of the plurality of periods utilized in the output of said single reference clock wherein the first phase difference is a multiple of the second phase difference;

determining a first reference period of a first reference clock of the plurality of reference clocks;

finding a first reference period in a second reference clock of the plurality of reference clocks lagging the first reference period of the first reference clock;

dividing the frequency of the first reference clock at a time point corresponding to the first reference period of the first reference clock in order to generate an output clock; and

dividing the frequency of the second reference clock at a time point corresponding to the first reference period of the second reference clock in order to generate another output clock.

2. The method of claim 1 wherein the first frequency is a multiple of the second frequency.

3. The method of claim 1 wherein a ratio of the first phase difference to the second phase difference is the same as a ratio of the plurality of reference clocks to the plurality of output clocks.

4. The method of claim 1 wherein when the first frequency is N times the second frequency, the method further comprises triggering periods of the second frequency according to the plurality of periods utilized in the output of one of the reference clocks at intervals of at least (N−

1) period.

5. The method of claim 1 wherein if the output of two reference clocks have the first phase difference of 360 degrees, the two reference clocks are essentially the same, and when using the two reference clocks to generate two corresponding output clocks, the two corresponding output clocks are triggered by different periods of one reference clock.

6. The method of claim 1 wherein the first reference clock leads the second reference clock by the first phase difference.

7. The method of claim 1 wherein the periods of each output clock are triggered by reference periods of a corresponding reference clock apart from other reference clocks by at least one or a plurality of periods of the corresponding reference clock wherein if a first period of one of the output clocks is triggered by a first reference period of a corresponding reference clock, a second period of said one of the output clocks would be triggered by a reference period lagging the first reference period by the first phase difference in a second reference clock, the second period of said one of the output clocks lagging the first period of said one of the output clocks by the second phase difference.

8. The method of claim 1 wherein two reference clocks are a third reference clock and a fourth reference clock, the method further comprising:

selecting a first reference period in the third reference clock;

in the fourth reference clock, stopping a reference period lagging the first reference period to generate a corresponding intermediate clock so that each reference period of the corresponding intermediate clock will lag the first reference period in the third reference clock; and

dividing the frequency of the third reference clock and the corresponding intermediate clock to generate two corresponding output clocks.

9. A multi-phase clock-generating circuit for generating two output clocks of the same frequency with a predetermined phase difference between each other, comprising:

a clock generator for generating two reference clocks having a same frequency that is a multiple greater than 1 of the frequency of the two output clocks, the two reference clocks having a predetermined reference phase difference between each other;

a phase interpolator for generating two corresponding output clocks wherein each period of these two output clocks is triggered by a corresponding reference period of one of the two reference clocks, which is apart from other reference periods of said one of the two reference clocks by at least one or a plurality of periods of said one of the two reference clocks;

a sequence triggering module for stopping a reference period of a second reference clock of said two reference clocks lagging a first reference period of a first reference clock of said two reference clocks to generate a corresponding intermediate clock; and

a frequency division module for dividing the frequency of the first reference clock and the corresponding intermediate clock to generate two corresponding output clocks;

wherein each reference period of the corresponding intermediate clock lags the first reference period of the first reference clock.

10. The multi-phase clock-generating circuit of claim 9 wherein the first reference clock leads the second reference clock by the predetermined reference phase difference.

11. The multi-phase clock-generating circuit of claim 9 wherein two reference clocks are a first reference clock and a second reference clock, and the phase interpolator comprises:

a sequence triggering module for finding in the second reference clock a first reference period lagging a first reference period of the first reference clock, and producing a corresponding reset signal at a time corresponding to the first reference period of the second reference clock;

a first frequency divider for generating an output clock by dividing the frequency of the first reference clock; and

a second frequency divider for generating the other output clock by dividing the frequency of the second reference clock after receiving the corresponding reset signal.

12. The multi-phase clock-generating circuit of claim 11 wherein the first frequency divider and the second frequency divider are triggered by rising edges of the first and second reference clocks respectively.

13. The multi-phase clock-generating circuit of claim 9 wherein the frequency of the reference clocks is a multiple of the frequency of the output clocks.

14. The multi-phase clock-generating circuit of claim 9 wherein the predetermined reference phase difference is plural times an output phase difference between outputs of the output clocks, and a ratio of the predetermined reference phase difference to the output phase difference is the same as a ratio of the frequency of the two reference clocks to the frequency of the output clocks.

15. A method of phase-splitting for generating two output clocks of the same frequency with a predetermined phase difference between each other, comprising:

generating a first reference clock having a frequency that is a multiple greater than 1 of a frequency of a corresponding output clock, a period of the corresponding output clock being substantially equal to an integer multiple of a reference period of the first reference clock;

triggering periods of different said two output clocks by the reference period of the corresponding reference clock to generate the two output clocks;

generating a second reference clock having the same clock frequency but a different phase as the first reference clock; and

triggering each period of a third output clock according to each period of the second reference clock;

wherein output of the third output clock is of the same frequency as said two output clocks and has the predetermined phase difference from said two output clocks.

16. The method of claim 15 wherein the predetermined phase difference of the two output clocks is between 0 and 360 degrees.

17. The method of claim 15 wherein the predetermined phase difference of the two output clocks is between 0 and 180 degrees or between 180 and 360 degrees.

18. The method of claim 15 wherein if the frequency of the reference clock is N times that of the corresponding output clock, the predetermined phase difference of the two output clocks is a multiple of 360/N degrees.

19. The method of claim 15 wherein frequency division is triggered by the reference period of the first reference clock to generate an output clock, a second reference period lagging the reference period of the first reference clock starting frequency division to generate another output clock.