Monolithic CMOS differential LNA with enhanced linearity
First Claim
1. A low noise amplifying (LNA) circuitry, having a differential input pair consisting of a positive input terminal and a negative input terminal, and a differential output pair consisting of a positive output terminal and a negative output terminal, comprising:
- a first cascode amplifying module;
a second cascade amplifying module;
a current source, controlled by a bias voltage level, for supplying current to the LNA circuitry;
a first resonant tank, coupled to the negative output terminal as output load; and
a second resonant tank, coupled to the positive output terminal as output load;
wherein,the first cascode amplifying module comprises;
a first transistor, having a channel width/length ratio r1,a second transistor, having a channel width/length ratio r2,a third transistor, having a channel width/length ratio r3, anda fourth transistor, having a channel width/length r4; and
the second cascade amplifying module comprises;
a first auxiliary transistor, having a channel width/length ratio r1′
,a second auxiliary transistor, having a channel width/length ratio r2′
,a third auxiliary transistor, having a channel width/length ratio r3′
, anda fourth auxiliary transistor, having a channel width/length ratio r4′
,wherein r1, r2, r3, r4, r1′
, r2′
, r3′
, and r4′
are selected such that andthe ratios of the first, second, third and fourth transistors are later than those of the first, second, third and fourth auxiliary transistors.
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Abstract
A low noise amplifier (LNA) is provided for a first block of a wireless receiver in a wireless communication system using CMOS technology. The LNA includes a first cascode amplifying module and a second cascode amplifying module, where an output signal of the first cascode amplifying module is fed to the second cascode amplifying module in order to cancel third-order intermodulation frequencies (IM3), such that input-referred third-order intercept point (IIP3) is increased and thus linearity of the LNA is improved.
22 Citations
13 Claims
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1. A low noise amplifying (LNA) circuitry, having a differential input pair consisting of a positive input terminal and a negative input terminal, and a differential output pair consisting of a positive output terminal and a negative output terminal, comprising:
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a first cascode amplifying module; a second cascade amplifying module; a current source, controlled by a bias voltage level, for supplying current to the LNA circuitry; a first resonant tank, coupled to the negative output terminal as output load; and a second resonant tank, coupled to the positive output terminal as output load; wherein, the first cascode amplifying module comprises; a first transistor, having a channel width/length ratio r1, a second transistor, having a channel width/length ratio r2, a third transistor, having a channel width/length ratio r3, and a fourth transistor, having a channel width/length r4; and the second cascade amplifying module comprises; a first auxiliary transistor, having a channel width/length ratio r1′
,a second auxiliary transistor, having a channel width/length ratio r2′
,a third auxiliary transistor, having a channel width/length ratio r3′
, anda fourth auxiliary transistor, having a channel width/length ratio r4′
,wherein r1, r2, r3, r4, r1′
, r2′
, r3′
, and r4′
are selected such thatand the ratios of the first, second, third and fourth transistors are later than those of the first, second, third and fourth auxiliary transistors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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Specification