Fractional-Bit Systems

• US 7,071,849 B2
• Filed: 03/31/2005
• Issued: 07/04/2006
• Est. Priority Date: 04/04/2004
• Status: Expired due to Fees

• Current Assignee: Guobiao Zhang
• Original Assignee: Guobiao Zhang
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Young, Brian
• Application Number:
  US10/907,381
• Publication Number:
  US 20050219077A1
• Time in Patent Office: 460 Days
• Field of Search: 341/105, 341/106, 341/97, 341/85, 341/62, 341/57, 341/56, 341/94, 375/286, 375/287
• US Class Current: 341/56
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H03M 7/165 Conversion to or from thermometric code

Abstract

The present invention abandons the conventional approach of incrementing bits-per-cell b by 1, but allows increments of states-per-cell N by as little as 1 between product generations. Because N is no longer an integral power of 2, b takes a fractional value, resulting in a fractional-bit system. In a fractional-bit system, cells are decoded in unit of word. By adjusting the word-width, the system efficiency can be optimized.

Claims

1. An N-ary fractional-bit system, comprising:

a first word and a second word, each comprising m N-ary cells, each N-ary cell having N possible states, where m is an integer representing the number of cells in a word and N is an integer representing the number of possible states for each cell;

means for selecting a word from said first and second words; and

an N-ary-to-binary encoder for converting said selected word into i binary bits, where i is an integer representing the number of binary outputs from said encoder and has a maximum value of n=INT[log₂(N^m)], with INT[x] representing the largest integer smaller than x;

whereby the average number of binary bits stored in each cell b is a non-integer and larger than 2.

2. The N-ary fractional-bit system according to claim 1, wherein said first and second words are located in a same unit-array.

3. The N-ary fractional-bit system according to claim 1, wherein said first and second words are located in different unit-arrays.

4. The N-ary fractional-bit system according to claim 1, wherein said first and second words are located in different chips.

5. The N-ary fractional-bit system according to claim 1, further comprising a plurality of cell-coding blocks for converting the read-out from each cell into a binary-like code.

6. The N-ary fractional-bit system according to claim 5, wherein said binary-like code is thermometer-code.

7. The N-ary fractional-bit system according to claim 5, wherein said binary-like code is quasibinary-code.

8. The N-ary fractional-bit system according to claim 1, wherein efficiency β

=INT[log₂(N^m)]/log₂(N^m)≧

90%.

9. The N-ary fractional-bit system according to claim 8, wherein:

A) for N=5, m≧

4;

B) for N=7, 11 or 15, m≧

3;

C) for N=6, 12, 13 or 14, m≧

2;

or

D) for N=9 or 10, m≧

1.

10. The N-ary fractional-bit system according to claim 1, wherein efficiency β

=INT[log₂(N^m)]/log₂(N^m) reaches a local maximum.

11. The N-ary fractional-bit system according to claim 10, wherein:

A) for N=5, m=4, 7, 10, 13, 16, 19, 22, 25, 28 or 32;

B) for N=6, m=2, 4, 7, 9, 12, 14, 16, 19, 21, 24, 26, 28 or 31;

C) for N=7, m=5, 10, 15, 20, 25 or 31;

D) for N=9, m=6, 12, 18, 24 or 30;

E) for N=10, m=4, 7, 10, 13, 16, 19, 22, 25 or 28;

F) for N=11, m=3, 5, 7, 9, 11, 14, 16, 18, 20, 22, 24, 27, 29 or 31;

G) for N=12, m=2, 4, 7, 9, 12, 14, 16, 19, 21, 24, 26, 28 or 31;

H) for N=13, m=3, 6, 10, 13, 16, 20, 23, 26 or 30;

I) for N=14, m=5, 10, 15, 20, 25 or 31;

or

J) for N=15, m=10, 21 or 32.

12. The N-ary fractional-bit system according to claim 1, wherein said system is a parallel-input system.

13. The N-ary fractional-bit system according to claim 12, wherein said cells are semiconductor memory cells.

14. The N-ary fractional-bit system according to claim 13, wherein said semiconductor memory is selected from a group of semiconductor memories including flash, EPROM, EEPROM, MRAM, FeRAM, DRAM, SRAM, variable-resistance memory, phase-change memory, Ovonyx unified memory, mask-programmable memory, diode memory, and antifuse memory.

15. The N-ary fractional-bit system according to claim 1, wherein said system is a serial-input system and further comprises a serial-to-parallel converting means.

16. The N-ary fractional-bit system according to claim 15, wherein said serial-input system is a disc drive.

17. The N-ary fractional-bit system according to claim 16, wherein said disc is selected from a group of disc storages including optical disc storage and magnetic disc storage.

18. The N-ary fractional-bit system according to claim 1, wherein said encoder is located in a same chip as said cells or a different chip from said cells.

19. The N-ary fractional-bit system according to claim 1, wherein said encoder is a programmable encoder.

20. The N-ary fractional-bit system according to claim 19, further comprising a processor or a program.