Low power analog to digital converter having reduced bias during an inactive phase

• US 7,071,863 B1
• Filed: 10/04/2005
• Issued: 07/04/2006
• Est. Priority Date: 12/06/2002
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Sutardja, Sehat, Aram, Farbod
• Primary Examiner(s): WAMSLEY, PATRICK G
• Application Number:
  US11/242,691
• Time in Patent Office: 273 Days
• Field of Search: 341/161, 341/143, 341/155, 341/172, 341/150, 323/282, 327/170, 327/337, 327/541, 330/9, 330/254, 331/17, 348/241, 360/66
• US Class Current: 341/161
• CPC Class Codes: H03M 1/002 Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
• CPC Class Codes: H03M 1/168 and delivering the same number of bits
• CPC Class Codes: H03M 1/442 using switched capacitors

Abstract

A circuit with reduced power consumption comprises first and second circuits that each have periodic active and inactive phases and that switch between the periodic active and inactive phases during operation. When the first circuit is in the active phase, the second circuit is in the inactive phase, and when the second circuit is in the active phase, the first circuit is in the inactive phase. A power supply communicates with the first and second circuits and generates first and second bias signals. The power supply selectively generates the first bias signal for the first circuit during the active phase of the first circuit, the second bias signal for the second circuit during the inactive phase of the second circuit, the second bias signal for the first circuit during the inactive phase of the first circuit, and the first bias signal for the second circuit during the active phase of the second circuit. The second bias signal is less than the first bias signal.

Claims

1. A circuit with reduced power consumption, comprising:

a first circuit that has periodic active and inactive phases and that switches between said periodic active and inactive phases during operation of said first circuit;

a second circuit that communicates with said first circuit, that has periodic active and inactive phases, and that switches between said periodic active and inactive phases during operation of said second circuit, wherein when said first circuit is in said active phase, said second circuit is in said inactive phase, and when said second circuit is in said active phase, said first circuit is in said inactive phase; and

a power supply that communicates with said first and second circuits and that generates first and second bias signals,

wherein said power supply selectively generates said first bias signal for said first circuit during said active phase of said first circuit, said second bias signal for said second circuit during said inactive phase of said second circuit, said second bias signal for said first circuit during said inactive phase of said first circuit, and said first bias signal for said second circuit during said active phase of said second circuit;

wherein said second bias signal is less than said first bias signal.

2. The circuit of claim 1 wherein said first bias signal is greater than zero and said second bias signal is zero.

3. The circuit of claim 1 wherein said first and second bias signals are greater than zero.

4. The circuit of claim 1 wherein said power supply is a variable power supply that selectively provides said first and second bias signals during said periodic active and inactive phases, respectively.

5. The circuit of claim 1 wherein said power supply includes two power supplies, and wherein only one of said two power supplies communicates with said first circuit during said inactive phase.

6. The circuit of claim 1 wherein said power supply includes a current source.

7. The circuit of claim 1 wherein said power supply includes a voltage source.

8. The circuit of claim 1 wherein said first circuit is one of a switched capacitor filter and an analog to digital converter.

9. The circuit of claim 1 wherein said periodic active and inactive phases of said first circuit are one of regular periodic or irregular periodic.

10. The circuit of claim 1 wherein said first bias signal is one of a square waveform, a stepped waveform having a first level followed by a second level, a linearly changing waveform, or a non-linearly changing waveform.

11. A circuit with reduced power consumption, comprising:

first circuit means for switching between periodic active and inactive phases during operation of said first circuit means;

second circuit means for communicating with said first circuit means and for switching between periodic active and inactive phases during operation of said second circuit means, wherein when said first circuit means is in said active phase, said second circuit means is in said inactive phase, and when said second circuit means is in said active phase, said first circuit means is in said inactive phase; and

power supply means for communicating with said first and second circuit means and for providing first and second bias signals,

wherein said power supply means selectively generates said first bias signal for said first circuit means during said active phase of said first circuit means, said second bias signal for said second circuit means during said inactive phase of said second circuit means, said second bias signal for said first circuit means during said inactive phase of said first circuit means, and said first bias signal for said second circuit means during said active phase of said second circuit means, and

wherein said second bias signal is less than said first bias signal.

12. The circuit of claim 11 wherein said first bias signal is greater than zero and said second bias signal is zero.

13. The circuit of claim 11 wherein said first and second bias signals are greater than zero.

14. The circuit of claim 11 wherein said power supply means is a variable power supply that selectively provides said first and second bias signals during said periodic active and inactive phases, respectively.

15. The circuit of claim 11 wherein said power supply means includes two power supplies, and wherein only one of said two power supplies communicates with said first circuit means during said inactive phase.

16. The circuit of claim 11 wherein said power supply means includes a current source.

17. The circuit of claim 11 wherein said power supply means includes a voltage source.

18. The circuit of claim 11 wherein said first circuit means is one of a switched capacitor filter and an analog to digital converter.

19. The circuit of claim 11 wherein said periodic active and inactive phases of said first circuit means are at least one of regular periodic and irregular periodic.

20. The circuit of claim 11 wherein said first bias signal is at least one of a square waveform, a stepped waveform having a first level followed by a second level, a linearly changing waveform, and a non-linearly changing waveform.

21. A method for reducing power consumption of a circuit, comprising:

switching a first circuit between periodic active and inactive phases during operation of said first circuit;

switching a second circuit between periodic active and inactive phases during operation of said second circuit, wherein when said first circuit is in said active phase, said second circuit is in said inactive phase and when said second circuit is in said active phase, said first circuit is in said inactive phase; and

selectively generating a first bias signal for said first circuit during said active phase of said first circuit, a second bias signal for said second circuit during said inactive phase of said second circuit, said second bias signal for said first circuit during said inactive phase of said first circuit, and said first bias signal for said second circuit during said active phase of said second circuit,

wherein said second bias signal is less than said first bias signal.

22. The method of claim 21 wherein said first bias signal is greater than zero and said second bias signal is zero.

23. The method of claim 21 wherein said first and second bias signals are greater than zero.

24. The method of claim 21 further comprising using a variable power supply to selectively provide said first and second bias signals during said periodic active and inactive phases, respectively.

25. The method of claim 21 further comprising:

providing two power supplies; and

connecting only one of said two power supplies to said first circuit during said inactive phase.

26. The method of claim 21 wherein said first circuit is one of a switched capacitor filter and an analog to digital converter.

27. The method of claim 21 wherein said first bias signal is one of a square waveform, a stepped waveform having a first level followed by a second level, a linearly changing waveform, or a non-linearly changing waveform.

28. The method of claim 21 wherein said periodic active and inactive phases of said first circuit are one of regular periodic or irregular periodic.

29. A multi-stage circuit with reduced power consumption, comprising:

a first stage including a first circuit that has periodic active and inactive phases and that switches between said periodic active and inactive phases during operation of said first circuit, and a first power supply that selectively generates a first bias signal for said first circuit during said active phase of said first circuit and a second bias signal for said first circuit during said inactive phase of said first circuit; and

a second stage including a second circuit that communicates with said first circuit, that has periodic active and inactive phases, and that switches between said periodic active and inactive phases during operation of said second circuit, and a second power supply that selectively generates said first bias signal for said second circuit during said active phase of said second circuit and said second bias signal for said second circuit during said inactive phase of said second circuit,

wherein when said first circuit is in said active phase, said second circuit is in said inactive phase, and when said second circuit is in said active phase, said first circuit is in said inactive phase, and wherein said second bias signal is less than said first bias signal.

30. The circuit of claim 29 wherein said first bias signal is greater than zero and said second bias signal is zero.

31. The circuit of claim 29 wherein said first and second bias signals are greater than zero.

32. The circuit of claim 29 wherein said first and second power supplies are variable power supplies that selectively provide said first and second bias signals during said periodic active and inactive phases, respectively.

33. The circuit of claim 29 wherein at least one of said first and second power supplies includes a current source.

34. The circuit of claim 29 wherein at least one of said first and second power supplies includes a voltage source.

35. The circuit of claim 29 wherein said first circuit is one of a switched capacitor filter and an analog to digital converter.

36. The circuit of claim 29 wherein said periodic active and inactive phases of said first circuit are one of regular periodic or irregular periodic.

37. The circuit of claim 29 wherein said first bias signal is one of a square waveform, a stepped waveform having a first level followed by a second level, a linearly changing waveform, or a non-linearly changing waveform.