Nonvolatile memory system, semiconductor memory and writing method

• US 7,072,222 B2
• Filed: 03/10/2005
• Issued: 07/04/2006
• Est. Priority Date: 07/09/1996
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi ULSI Engineering Corp, Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Ishii, Tatsuya, Tsuchiya, Osamu, Miwa, Hitoshi, Kubono, Shooji
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Nguyen, Hien
• Application Number:
  US11/075,813
• Publication Number:
  US 20050157550A1
• Time in Patent Office: 481 Days
• Field of Search: 365/185.01, 365/185.24, 365/189.05, 365/185.29, 365/185.02, 365/230.08
• US Class Current: 365/185.24
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2216/18 Flash erasure of all the cells in an array, sector or block simultaneously

Abstract

A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.

Claims

1. A nonvolatile memory comprising:

a plurality of nonvolatile memory cells each of which has an arbitrary one of a programmed state and an erased state;

a plurality of input/output terminals;

a command decode circuit which is capable of decoding an arbitrary one of commands received via said plurality of input/output terminals;

a voltage generator;

a plurality of word lines; and

a control circuit,

wherein in performing an erase operation in response to decoding an erase command by said command decode circuit, said control circuit controls shifting a state of all of said nonvolatile memory cells coupled to one word line to said erased state,

wherein in performing a program operation in response to decoding a write command, which is accompanied with address information and data, by said command decode circuit, said control circuit controls selection of one word line in accordance with said address information, supply of a program voltage generated by said voltage generator to said one word line, and storage of said data into first ones of said nonvolatile memory cells coupled to said one word line,

wherein said write command is capable of being accompanied with 512 byte data,

wherein all of said first ones of said nonvolatile memory cells coupled to said one word line have said erased state before performing said program operation, and

wherein another one of said nonvolatile memory cells coupled to said one word line has said programmed state before performing said program operation and has said programmed state after performing said program operation.

2. A nonvolatile memory according to claim 1, further comprising a plurality of buffer circuits,

wherein said plurality of buffer circuits are coupled to said input/output terminals, and are capable of storing said data temporarily.

3. A nonvolatile memory according to claim 2,

wherein said control circuit reads out operation steps from a program memory for controlling said program operation by executing said operation steps.

4. A nonvolatile memory according to claim 3,

wherein the number of nonvolatile memory cells coupled to one word line is more than 4096.

5. A nonvolatile memory according to claim 1,

wherein each of said plurality of nonvolatile memory cells is structured by one transistor.

6. A nonvolatile memory according to claim 1, wherein the nonvolatile memory is structured on one semiconductor substrate.

7. A nonvolatile memory comprising:

a plurality of nonvolatile memory cells, each of which has an arbitrary one of a programmed state and an erased state;

a plurality of input/output terminals;

a command register which is capable of storing an arbitrary one of commands received via said plurality of input/output terminals;

a voltage generator;

a plurality of word lines; and

a sequencer,

wherein in performing an erase operation in response to decoding an erase command, said sequencer controls moving of states of said nonvolatile memory cells coupled to one word line to said erased state,

wherein in performing a program operation in response to a write command, which is accompanied with address information and data, received via said input/output terminals, said sequencer controls selection of one word line in accordance with said address information, supply of a program voltage generated by said voltage generator to said one word line, and moving of states of said nonvolatile memory cells coupled to said one word line from said erased state to said programmed state in accordance with said data,

wherein said write command is capable of being accompanied with 512 byte data, and

wherein said sequencer allows performing a first program operation in response to said write command accompanied with said address information, wherein in said first program operation, said sequencer controls selection of a first word line and movement of states of first ones of said nonvolatile memory cells coupled to said first word line to said program state, after performing a second program operation in response to a write command accompanied with said address information, wherein in said second program operation, said sequencer controls selection of said first word line and movement of states of second ones, which are not the same nonvolatile memory cells as said first ones, of said nonvolatile memory cells coupled to said first word line to said program state, without performing said erase operation in response to said erase command for moving states of said nonvolatile memory cells coupled to said first word line into said erased state.

8. A nonvolatile memory according to claim 7,

wherein said sequencer executes operation steps fetched from a program memory for performing said program operation and said erase operation.

9. A nonvolatile memory according to claim 8,

wherein said program memory is structured by a ROM.

10. A nonvolatile memory according to claim 7,

wherein each of said plurality of nonvolatile memory cells is structured by one transistor.

11. A nonvolatile memory according to claim 7,

wherein said nonvolatile memory is structured on one semiconductor substrate.

12. A nonvolatile memory according to claim 7, further comprising a command decoder,

wherein said command decoder decodes said arbitrary one of commands stored in said command register.