Semiconductor memory device and multi-chip module comprising the semiconductor memory device
First Claim
1. A semiconductor memory device formed of a semiconductor chip for being overlaid onto a surface of another semiconductor chip to be electrically connected therewith, comprising:
- a memory cell array including a plurality of memory cell array blocks each having a plurality of memory cells, each of the memory cell array blocks having a predetermined basic capacity;
a control circuit, which is formed on the same semiconductor chip as the memory cell array is formed, for controlling reading and writing from and into the memory cells in the memory cell array;
a common chip connector portion having terminals formed on the control circuit for connecting to another semiconductor chip; and
a plurality of individually provided chip connector portions, each individually provided for each of the memory cell array blocks, each having terminals formed on each of the memory cell array blocks, all of the plurality of individually provided chip connector portions having a same configuration.
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Accused Products
Abstract
In a semiconductor memory device composed of a semiconductor chip and overlaid to a surface of another semiconductor chip so as to connect together, a control circuit provided in the semiconductor memory device is provided with a chip connector portion having a plurality of pads. The chip connector portion is formed to have a configuration corresponding to the maximum capacity of the memory cell array provided in the semiconductor memory device, and the location and the number of the pads are invariably determined even when the memory cell array has a capacity less than the maximum capacity. The control circuit incorporating the chip connector portion is also invariably determined so as to control reading and writing data from and into the memory cell array having the maximum capacity, regardless of the capacity of the memory cell array provided.
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Citations
8 Claims
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1. A semiconductor memory device formed of a semiconductor chip for being overlaid onto a surface of another semiconductor chip to be electrically connected therewith, comprising:
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a memory cell array including a plurality of memory cell array blocks each having a plurality of memory cells, each of the memory cell array blocks having a predetermined basic capacity; a control circuit, which is formed on the same semiconductor chip as the memory cell array is formed, for controlling reading and writing from and into the memory cells in the memory cell array; a common chip connector portion having terminals formed on the control circuit for connecting to another semiconductor chip; and a plurality of individually provided chip connector portions, each individually provided for each of the memory cell array blocks, each having terminals formed on each of the memory cell array blocks, all of the plurality of individually provided chip connector portions having a same configuration. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification