Periodic interface calibration for high speed communication
First Claim
Patent Images
1. A signal interface, comprising:
- a set of signal lines having N+1 signal lines, where N is an integer;
N+1 receivers coupled to respective signal lines in the set of signal lines establishing a set of N+1 signal paths with the set of signal lines;
an N line bus;
a line maintenance circuit; and
a switch in the N+1 signal paths, and control logic for the switch, which selectively routes N signal paths in the set to the N line bus and signal path (n) in the set to the line maintenance circuit, where (n) is changed according to a pattern to selectively maintain signal paths in the set of N+1 signal paths while enabling data flow on N signal paths in the set to the N line bus;
wherein for a change of (n) by switching a first particular signal path from routing to the line maintenance circuit to routing to a line in the N line bus, and a second particular signal path from routing to the line in the N line bus to the line maintenance circuit, the control logic controls the switch so that reception of data from the line in the N line bus is uninterrupted; and
wherein the receivers are responsive to respective receive clocks produced by adjustable clock generators, and said line maintenance circuit sets the adjustable clock generators in response to a calibration data pattern on the signal path coupled to the line maintenance circuit.
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Abstract
A high-speed communication interface manages a parallel bus having N bus lines. N+1 communication lines are established. A maintenance operation is performed on one of the N+1 communication lines, while N of the N+1 communication lines is available for data from the N line bus. The communication line on which the maintenance operation is performed, is changed after the operation is complete, so that all of the N+1 communication lines are periodically maintained, without interfering with communications on N of the N+1 communication lines.
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Citations
48 Claims
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1. A signal interface, comprising:
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a set of signal lines having N+1 signal lines, where N is an integer; N+1 receivers coupled to respective signal lines in the set of signal lines establishing a set of N+1 signal paths with the set of signal lines; an N line bus; a line maintenance circuit; and a switch in the N+1 signal paths, and control logic for the switch, which selectively routes N signal paths in the set to the N line bus and signal path (n) in the set to the line maintenance circuit, where (n) is changed according to a pattern to selectively maintain signal paths in the set of N+1 signal paths while enabling data flow on N signal paths in the set to the N line bus;
wherein for a change of (n) by switching a first particular signal path from routing to the line maintenance circuit to routing to a line in the N line bus, and a second particular signal path from routing to the line in the N line bus to the line maintenance circuit, the control logic controls the switch so that reception of data from the line in the N line bus is uninterrupted; andwherein the receivers are responsive to respective receive clocks produced by adjustable clock generators, and said line maintenance circuit sets the adjustable clock generators in response to a calibration data pattern on the signal path coupled to the line maintenance circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A signal interface, comprising:
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a set of signal lines having N+1 signal lines, where N is an integer; N+1 receivers coupled to respective signal lines in the set of signal lines establishing a set of N+1 signal paths with the set of signal lines; an N line bus; a line maintenance circuit; and a switch in the N+1 signal paths, and control logic for the switch, which selectively routes N signal paths in the set to the N line bus and signal path (n) in the set to the line maintenance circuit, where (n) is changed according to a pattern to selectively maintain signal paths in the set of N+1 signal paths while enabling data flow on N signal paths in the set to the N line bus ,wherein for a change of (n) by switching a first particular signal path from routing to the line maintenance circuit to routing to a line in the N line bus, and a second particular signal path from routing to the line in the N line bus to the line maintenance circuit, the control logic controls the switch so that during a settling interval, the first and second particular signal paths both carry data from the line in the N line bus, and then after the settling interval the second particular signal path is coupled to the line maintenance circuit; and wherein the receivers are responsive to respective receive clock signals produced by adjustable clock generators, and said line maintenance circuit sets the adjustable clock generators in response to a calibration data pattern on the signal path coupled to the line maintenance circuit.
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11. A signal interface, comprising:
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an N line bus; a set of signal lines having N+1 signal lines, where N is an integer; N+1 transmitters coupled to respective signal lines in the set of signal lines establishing a set of N+1 signal paths with the set of signal lines; a line maintenance circuit; and a switch in the N+1 signal paths, and control logic for the switch, which selectively routes N signal paths in the set from the N line bus to N signal lines in the set of signal lines, and routes signal path (n) in the set from the line maintenance circuit to signal line (n) in the set of signal lines, where (n) is changed according to a pattern to selectively perform maintenance on signal paths in the set of N+1 signal paths while enabling data flow on N signal paths in the set from the N line bus;
wherein for a change of (n) by switching a first particular signal path from routing to the line maintenance circuit to routing to a line in the N line bus, and a second particular signal path from routing to the line in the N line bus to the line maintenance circuit, the control logic controls the switch so that transmission of data from the line in the N line bus is uninterrupted, wherein receivers coupled to the signal lines are responsive to respective receive clock signals produced by corresponding adjustable clock generators, and a line maintenance circuit coupled with the receivers sets the adjustable clock generators in response to a calibration data pattern on the signal path coupled to the line maintenance circuit coupled with the receivers. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A signal interface, comprising:
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an N line bus; a set of signal lines having N+1 signal lines, where N is an integer; N+1 transmitters coupled to respective signal lines in the set of signal lines establishing a set of N+1 signal paths with the set of signal lines; a line maintenance circuit; and a switch in the N+1 signal paths, and control logic for the switch, which selectively routes N signal paths in the set from the N line bus to N signal lines in the set of signal lines, and routes signal path (n) in the set from the line maintenance circuit to signal line (n) in the set of signal lines, where (n) is changed according to a pattern to selectively perform maintenance on signal paths in the set of N+1 signal paths while enabling data flow on N signal paths in the set from the N line bus for a change of (n) by switching a first particular signal path from routing from the line maintenance circuit to routing to a line in the N line bus, and a second particular signal path from routing to the line in the N line bus from the line maintenance circuit, the control logic controls the switch so that during a settling interval, the first and second particular signal paths both carry data to the line in the N line bus, and then after the settling interval the second particular signal path is coupled to the line maintenance circuit; and wherein receivers coupled to the signal lines are responsive to respective receive clock signals produced by corresponding adjustable clock generators, and a line maintenance circuit coupled with the receivers sets the adjustable clock generators in response to a calibration data pattern on the signal path coupled to the line maintenance circuit coupled with the receivers.
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23. A communication system for inter-chip signals, comprising:
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a first integrated circuit, a second integrated circuit, and a set of N+1 communications lines between the first and second integrated circuits; the first integrated circuit comprising a first N line bus, where N is an integer; a set of transmitter signal lines having N+1 transmitter signal lines coupled to respective communications lines in the set of N+1 communications lines; N+1 transmitters coupled to respective transmitter signal lines in the set of transmitter signal lines establishing a set of N+1 transmitter signal paths with the set of transmitter signal lines; a calibration signal source; and a switch in the N+1 transmitter signal paths, and first control logic which selectively routes N transmitter signal paths in the set from the first N line bus to N transmitter signal lines in the set of signal lines, and routes transmitter signal path (n) in the set from the calibration signal source to one transmitter signal line in the set of transmitter signal lines, where (n) is changed according to a pattern to selectively supply calibration signals on communication lines in the set of N+1 communication lines while enabling data flow on N communication lines in the set from the first N line bus; and the second integrated circuit comprising a set of receiver signal lines having N+1 receiver signal lines coupled to respective communications lines in the set of N+1 communications lines; N+1 receivers coupled to respective receiver signal lines in the set of receiver signal lines establishing a set of N+1 receiver signal paths with the set of receiver signal lines; a second N line bus; a calibration circuit; and a switch in the N+1 receiver signal paths, and second control logic, which selectively routes N receiver signal paths in the set to the second N line bus and receiver signal path (n) in the set to the calibration circuit, where (n) is changed according to the pattern to selectively calibrate receiver signal paths in the set of N+1 receiver signal paths while enabling data flow on N receiver signal paths in the set to the second N line bus; and wherein the receivers are responsive to respective receive clock signals produced by adjustable clock generators, and said line maintenance circuit sets the adjustable clock generators in response to a calibration data pattern on the signal path coupled to the calibration circuit; and control logic on at least one of the first and second integrated circuits;
wherein for a change of (n) by switching a first particular signal path from routing between the calibration signal source and the calibration circuit to routing to between lines in the first and second N line buses, and a second particular signal path from routing between lines in the first and second N line buses to routing between the calibration signal source and the calibration circuit, the control logic controls the switch so that transmission of data from between the lines in the first and second N line buses is uninterrupted. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
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34. A communication system for inter-chip signals, comprising:
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a first integrated circuit, a second integrated circuit, and a set of N+1 communications lines between the first and second integrated circuits; the first integrated circuit comprising; a first N line bus, where N is an integer; a set of transmitter signal lines having N+1 transmitter signal lines coupled to respective communications lines in the set of N+1 communications lines; N+1 transmitters coupled to respective transmitter signal lines in the set of transmitter signal lines establishing a set of N+1 transmitter signal paths with the set of transmitter signal lines; a calibration signal source; and a switch in the N+1 transmitter signal paths, and first control logic which selectively routes N transmitter signal paths in the set from the first N line bus to N transmitter signal lines in the set of signal lines, and routes transmitter signal path (n) in the set from the calibration signal source to one transmitter signal line in the set of transmitter signal lines, where (n) is changed according to a pattern to selectively supply calibration signals on communication lines in the set of N+1 communication lines while enabling data flow on N communication lines in the set from the first N line bus; and the second integrated circuit comprising; a set of receiver signal lines having N+1 receiver signal lines coupled to respective communications lines in the set of N+1 communications lines; N+1 receivers coupled to respective receiver signal lines in the set of receiver signal lines establishing a set of N+1 receiver signal paths with the set of receiver signal lines; a second N line bus; a calibration circuit; and a switch in the N+1 receiver signal paths, and second control logic, which selectively routes N receiver signal paths in the set to the second N line bus and receiver signal path (n) in the set to the calibration circuit, where (n) is changed according to the pattern to selectively calibrate receiver signal paths in the set of N+1 receiver signal paths while enabling data flow on N receiver signal paths in the set to the second N line bus; and wherein the receivers are responsive to respective receive clock signals produced by adjustable clock generators, and said line maintenance circuit sets the adjustable clock generators in response to a calibration data pattern on the signal path coupled to the calibration circuit, and wherein for a change of (n) by switching a first particular transmitter signal path from routing from the calibration signal source to routing from a line in the first N line bus, and a second particular transmitter signal path from routing from the line in the first N line bus to routing from the calibration signal source, the first control logic controls the switch in the N+1 transmitter signal paths so that during a settling interval, the first and second particular transmitter signal paths both carry data from the line in the first N line bus, and then after the settling interval the second particular signal path is routed from the calibration signal source.
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35. A method for managing a high speed communication interface for a parallel bus having N bus lines, where N is an integer, comprising:
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establishing N+1 communication lines; performing a maintenance operation on communication line (n) of the N+1 communications lines and enabling paths from the N bus lines on N of the N+1 communications lines, wherein receivers on the N+1 communications lines are responsive to respective receive clock signals produced by adjustable clock generators, and said maintenance operation sets the adjustable clock generators in response to a calibration data pattern transmitted on the communication line (n); after performing the maintenance operation on communication line (n) of the N+1 communications lines, changing (n) and performing a maintenance operation a next communication line of the N+1 communication lines; and
for a changing (n) to switch a first particular communication line from subject of the maintenance operation to communicating from a line on the N line bus, and a second particular communication line from communicating from the line on the N line bus to subject of the maintenance operation, routing the first and second particular communication lines so that both carry data from the line in the N line bus during a settling interval, and then after the settling interval performing the maintenance operation on the second particular communication line. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42, 43)
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44. A signal interface, comprising:
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a set of signal lines; a set of receivers coupled to respective signal lines in the set of signal lines; a bus comprising a set of bus lines; a line maintenance circuit; and a switch coupled to the set of receivers, to the bus and to the line maintenance circuit, and control logic for the switch, which selectively routes signals in parallel from receivers in the set of receivers to bus lines in the set of bus lines and to the line maintenance circuit, where the receiver in the set of receivers routed to the line maintenance circuit is changed according to a pattern to selectively maintain signal paths over said set of signal lines without interrupting data flow from the set of receivers from the set of signal lines; and wherein the receivers are responsive to respective receive clock signals produced by adjustable clock generators, and said line maintenance circuit sets the adjustable clock generators in response to a calibration data pattern on the signal path coupled to the calibration circuit.
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45. A transmission circuit on an integrated circuit, comprising:
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a line maintenance circuit to output a line maintenance signal; a set of transmitters coupled to receive a first set of signals and the line maintenance signal, and to output a second set of signals, wherein the second set of signals includes the first set of signals and the maintenance signal; and a switch coupled to the set of transmitters and a control logic for the switch, to selectively route the first set of signals and the line maintenance signal in parallel to the set of transmitters, where the transmitter in the set of transmitters routed to the line maintenance circuit is changed according to a pattern to selectively maintain the second set of signals from the set of transmitters and to permit the maintenance signal to be used as a calibration signal, the transmitter in the set of transmitters routed to the line maintenance circuit is changed without interruption of transmission of the first set of signals, wherein receivers adapted to receive the second set of signals are responsive to respective receive clock signals produced by corresponding adjustable clock generators, and a line maintenance circuit coupled with the receivers sets the adjustable clock generators in response to a calibration data pattern in the maintenance signal.
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46. A receiver circuit on an integrated circuit, comprising:
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means for receiving a first set of signals and a line maintenance signal, and to output a second set of signals; means for calibrating the means for receiving without interrupting the outputting of the second set of signals, the means for calibrating coupled to receive the line maintenance signal; means for routing the first set of signals and the line maintenance signal in parallel from the means for receiving, wherein the routing changes according to a pattern to selectively maintain the second set of signals and to permit the maintenance signal to be used as a maintenance signal for maintaining different portions of the means for receiving; and wherein the maintenance signal comprises a calibration data pattern, and the means for receiving includes receivers that are responsive to respective receive clock signals produced by adjustable clock generators, and said means for calibrating sets the adjustable clock generators in response to the calibration data pattern.
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47. A signal interface, comprising:
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a set of signal lines having N+1 signal lines, where N is an integer; N+1 receivers coupled to respective signal lines in the set of signal lines establishing a set of N+1 signal paths with the set of signal lines; an N line bus; a line maintenance circuit; and a switch in the N+1 signal paths, and control logic for the switch, which selectively routes N signal paths in the set to the N line bus and signal path (n) in the set to the line maintenance circuit, where (n) is changed according to a pattern to selectively maintain signal paths in the set of N+1 signal paths while enabling data flow on N signal paths in the set to the N line bus;
wherein the line maintenance circuit performs calibration of the receiver coupled to signal path (n) routed to the line maintenance circuit, independent of the data flow on the N line bus; andwherein the receivers are responsive to respective receive clock signals produced by adjustable clock generators, and said line maintenance circuit sets the adjustable clock generators in response to a calibration data pattern on the signal path coupled to the calibration circuit.
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48. A signal interface, comprising:
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an N line bus; a set of signal lines having N+1 signal lines, where N is an integer; N+1 transmitters coupled to respective signal lines in the set of signal lines establishing a set of N+1 signal paths with the set of signal lines; a line maintenance circuit; and a switch in the N+1 signal paths, and control logic for the switch, which selectively routes N signal paths in the set from the N line bus to N signal lines in the set of signal lines, and routes signal path (n) in the set from the line maintenance circuit to signal line (n) in the set of signal lines, where (n) is changed according to a pattern to selectively perform maintenance on signal paths in the set of N+1 signal paths while enabling data flow on N signal paths in the set from the N line bus, independent of the data flow on the N line bus;
wherein receivers coupled to the signal lines are responsive to respective receive clock signals produced by corresponding adjustable clock generators, and a line maintenance circuit coupled with the receivers sets the adjustable clock generators in response to a calibration data pattern on the signal path coupled to the line maintenance circuit coupled with the receivers.
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Specification