Adaptive direct conversion receiver

• US 7,072,424 B2
• Filed: 04/23/2002
• Issued: 07/04/2006
• Est. Priority Date: 04/23/2002
• Status: Expired due to Fees

• Current Assignee: Kyocera Corporation
• Original Assignee: Kyocera Wireless Corporation (Kyocera Corporation)
• Inventors: Forrester, Tim
• Primary Examiner(s): Bocure, Tesfaldet
• Assistant Examiner(s): Panwalkar, Vineeta S.
• Application Number:
  US10/131,166
• Publication Number:
  US 20030198306A1
• Time in Patent Office: 1,533 Days
• Field of Search: 375/377, 375/224, 375/327, 375/316, 375/326, 375/345, 455/324, 455/200
• US Class Current: 375/316
• CPC Class Codes: H04B 1/109 by improving strong signal performance of the receiver when strong unwanted signals are present at the receiver input
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22
• CPC Class Codes: H04L 1/0001 Systems modifying transmission characteristics according to link quality, e.g. power backoff adaptive data allocation for multicarrier modulation H04L5/0044; controlling transmission power for radio systems H04W52/04

Abstract

A method and apparatus is disclosed for improving performance of a communication receiver. In one embodiment a method and apparatus is configured to process a communication signal by adjusting the amplification level of the signal and monitoring for a corresponding change in the error rate which indicates the increased error rate is caused by an interference or jammer signal. A method and apparatus is disclosed which reduces the error rate if the error rate can be reduced by activating error reducing operations. In one embodiment current flow to a mixer is increased to reduce the error rate. The apparatus may be further configured to periodically monitor the error rate during periods when error reducing operations are active. If the monitoring determines the error rate has sufficiently decreased then the receiver operation is restored to normal operation. Phase offset adjustment may also occur to further reduce the error rate.

Claims

1. A method for determining a cause of a high error rate in a receiver configured to receive and process a signal, the method comprising:

demodulating a signal received by a receiver to create a baseband signal;

calculating an error rate at a first time;

adjusting an amplification level applied to the signal as follows;

increasing the amplification level applied to the signal; and

decreasing the amplification level applied to the baseband signal;

calculating an error rate at a second time after the adjusting, wherein the error rate is derived from the signal at a second time;

comparing the error rate at the first time to the error rate at the second time; and

determining that the high error rate is caused by an interference signal if the error rate at the second time is different than the error rate at the first time.

2. The method of claim 1, wherein adjusting an amplification level applied to the signal comprises increasing the amplification level of a low noise amplifier.

3. An apparatus for determining if an increase in an error rate of a received signal is caused by an interference signal, the apparatus comprising:

an amplifier configured to amplify the received signal;

an amplifier control module in communication with the amplifier and configured to change the level of amplification performed by the amplifier;

an error detection module configured to calculate the error rate of the received signal;

wherein the amplifier controller;

receives the error rate from the error detection module during a first period and a second period;

changes the level of amplification at the first period as compared to the second period;

compares the error rate calculated during the first period to the error rate calculated during the second period to determine if an increase in the error rate is from an interference signal; and

a demodulator control unit configured to increase current flow to a demodulator during periods when the error rate of the received signal is caused by an interference signal.

4. The apparatus of claim 3, wherein the interference signal comprises a second order blocking product.

5. The apparatus of claim 3, wherein the controller comprises a digital signal processor.

6. The apparatus of claim 3, wherein the apparatus operates in conjunction with a direct conversion receiver to reduce the bit error rate of the direct conversion receiver.

7. A computer program product comprising a computer readable medium having computer program logic recorded thereon for error rate analysis and reduction, comprising:

computer program code logic configured to analyze a signal, which has been amplified and demodulated, to determine at a first time a rate of error associated with the signal;

computer program code logic configured to modify a gain level applied to the signal;

computer program control logic configured to analyze the signal to determine at a second time after gain level modification a rate of error associated with the signal; and

computer program control logic configured to increase power provided to a demodulator if the error rate changed as a result of the modification to the gain level, the computer program control logic further configured to increase current consumption by a mixer to reduce second order blocking products.

8. The computer readable medium of claim 7, wherein the computer program code logic configured to modify a gain level comprises computer program code logic configured to modify a gain level applied to the signal by a low noise amplifier.

9. The computer readable medium of claim 7, further including computer program code logic configured to monitor the error rate and reduce the power provided to the demodulator if the monitoring reveals a reduction in the error rate to an acceptable level.