Adaptive defect based testing

• US 7,073,107 B2
• Filed: 02/28/2003
• Issued: 07/04/2006
• Est. Priority Date: 02/28/2003
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Rajagopalan, Vijayashanker, Madge, Robert
• Primary Examiner(s): Lamarre, Guy
• Assistant Examiner(s): Trimmings, John P.
• Application Number:
  US10/377,426
• Publication Number:
  US 20040181717A1
• Time in Patent Office: 1,222 Days
• Field of Search: 714/25, 714/724, 714/799, 438/14, 438/17, 324/500, 702/117
• US Class Current: 714/724
• CPC Class Codes: G01R 31/01 Subjecting similar articles in turn to test, e.g. "go/no-go" tests in mass production; Testing objects at points as they pass through a testing station testing of cables continuously passing the testing apparatus G01R31/59; testing dielectric strength or breakdown voltage G01R31/12
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: G01R 31/31718 Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis mechanical aspects G01R31/2808, G01R31/2851
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information

Abstract

A method of testing integrated circuits. Each of the integrated circuits is tested with a first test at a first level of testing at a preceding testing step in a fabrication cycle of the integrated circuits to produce first test results associated with a first characteristic of the integrated circuits. The first test results are recorded with associated integrated circuit identification information. The integrated circuits are logically subdivided into bins based at least in part on the associated integrated circuit identification information. A defectivity value is calculated for each bin of subdivided integrated circuits based at least in part on the first test results recorded with the associated integrated circuit identification information. The integrated circuits within each of the bins are tested with a second test at a second level of testing at a succeeding testing step in the fabrication cycle of the integrated circuits to produce second test results associated with a second characteristic of the integrated circuits. The second characteristic is related to the first characteristic and the second level of testing is varied from bin to bin based at least in part on the defectivity value for the bin being tested.

Claims

1. A method of testing integrated circuits, the method comprising the steps of:

performing on each of the integrated circuits a first test at a first level of testing at a preceding testing step in a fabrication cycle of the integrated circuits to produce first test results associated with a first characteristic of the integrated circuits,

recording the first test results with associated integrated circuit identification information,

logically subdividing the integrated circuits into bins based at least in part on the associated integrated circuit identification information and not on the first test results,

calculating a defectivity value for each bin of subdivided integrated circuits based at least in part on the first test results recorded with the associated integrated circuit identification information,

performing on the integrated circuits within each of the bins a second test at a second level of testing at a succeeding testing step in the fabrication cycle of the integrated circuits to produce second test results associated with a second characteristic of the integrated circuits, where the second characteristic is related to the first characteristic and the second level of testing is varied from bin to bin based at least in part on the defectivity value for the bin being tested, where

the second level of testing is a normal level of testing, based on the defectivity being substantially equal to a predetermined value,

the second level of testing is a reduced level of testing, based on the defectivity being less than the predetermined value, and

the second level of testing is an elevated level of testing, based on the defectivity being more than the predetermined value,

calculating a second running defectivity for the bin during the second test, and

dynamically adjusting the second level of testing for the bin based at least in part on the second running defectivity.

2. The method of claim 1, wherein the preceding test is an inline test and the succeeding test is at least one of wafer sort and final test.

3. The method of claim 1, wherein the preceding test is wafer sort and the succeeding test is final test.

4. The method of claim 1, wherein the first test and the second test are the same test.

5. The method of claim 1, wherein the first test is at least one of functional test, Iddq, scan, transition delay fault, oxide break down voltage, Vddmin, Fmax, I/O leakage, and memory test.

6. The method of claim 1, wherein the succeeding testing step is stress testing.

7. The method of claim 1, wherein the second level of testing is no testing of the second test at all, based on the defectivity being less than the predetermined value.

8. The method of claim 1, wherein the bins are based on a substrate region identification as recorded in the associated integrated circuit identification information.

9. The method of claim 1, wherein the bins are based on a substrate identification as recorded in the associated integrated circuit identification information.

10. The method of claim 1, wherein the bins are based on a lot identification as recorded in the associated integrated circuit identification information.

11. The method of claim 1, wherein the preceding testing step comprises a plurality of first tests at a plurality of first levels and the succeeding testing step comprises a plurality of second tests at a plurality of second levels.

12. The method of claim 1, wherein the preceding testing step comprises a plurality of first tests at a plurality of first levels and the succeeding testing step comprises a plurality of second tests at a plurality of second levels and the binning of the integrated circuits is different for different second tests.

13. The method of claim 1, wherein the preceding testing step is wafer sort and the first test comprises both leakage/bridging and frequency/VDD, and the succeeding testing step is stress testing and the second test comprises both enhanced voltage stress testing and dynamic voltage stress testing, and the first test results for an individual integrated circuit are statistically compared to the first test results for other integrated circuits within the same bin to determine the second levels of testing.

14. The method of claim 13, wherein the leakage/bridging and the frequency/VDD first test results for the individual integrated circuit are statistically similar to the leakage/bridging and the frequency/VDD first test results for the other integrated circuits within the same bin, and the second levels of testing are reduced to no testing.

15. The method of claim 13, wherein the leakage/bridging first test results for the individual integrated circuit are statistically similar to the leakage/bridging first test results for the other integrated circuits within the same bin, and the frequency/VDD first test results for the individual integrated circuit are not statistically similar to the frequency/VDD first test results for the other integrated circuits within the same bin, and the second level of testing for enhanced voltage stress testing is reduced to no testing and the second level of testing for dynamic voltage stress testing is a normal level of testing.

16. The method of claim 13, wherein the leakage/bridging first test results for the individual integrated circuit are not statistically similar to the leakage/bridging first test results for the other integrated circuits within the same bin, and the frequency/VDD first test results for the individual integrated circuit are statistically similar to the frequency/VDD first test results for the other integrated circuits within the same bin, and the second level of testing for enhanced voltage stress testing is a normal level of testing and the second level of testing for dynamic voltage stress testing is reduced to no testing.