Apparatus and method for saturating decoder values

• US 7,073,118 B2
• Filed: 09/17/2001
• Issued: 07/04/2006
• Est. Priority Date: 09/17/2001
• Status: Expired due to Term

• Current Assignee: ARRIS Enterprises LLC (CommScope Holding Company, Inc.)
• Original Assignee: Digeo Incorporated (CommScope Holding Company, Inc.)
• Inventors: Shah, Manish, Greenberg, Mark
• Primary Examiner(s): Chung, Phung M.
• Application Number:
  US09/955,547
• Publication Number:
  US 20030135813A1
• Time in Patent Office: 1,751 Days
• Field of Search: 714/796, 714/795, 714/794, 714/792, 375/262, 375/265, 375/341
• US Class Current: 714/796
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/4382 Demodulation or channel decoding, e.g. QPSK demodulation analog front ends or means for connecting modulators, demodulators or transceivers to a transmission line H04L27/0002
• CPC Class Codes: H04N 21/4383 Accessing a communication channel
• CPC Class Codes: H04N 5/4446 IF amplifier circuits specially adapted for B&W TV RF amplifiers in general H03F3/189
• CPC Class Codes: H04N 5/455 Demodulation-circuits

Abstract

In one embodiment of the invention, during add-compare-select computations, the output of the adders is guaranteed to be a positive value because the only time normalization logic subtracts a normalization amount is when all accumulators are greater than the normalization amount. As such, the detection of overflow is greatly simplified. Overflow in the add-compare-select unit may be indicated simply by the value of the most significant bit (“MSB”) (i.e., the sign bit) of the result. If the MSB of the result of the adder is set then, in one embodiment, the output of the adder gets forced the maximum possible value given the number of bits. For example, this value will be forced to 7h7f if the value is represented by 7-bits. That is to say, if an overflow is detected, then the accumulator is saturated to the maximum value.

Claims

1. An apparatus comprising:

a first adder to add a first branch metric value to a previous path metric value to generate a first path metric value; and

saturating logic to detect a saturating condition when a most signiflcaflt bit (lvlSBTM) of said first path metjic value is a specified valuet, the saturating logic arranged to select the first path metric value to form a first state metric when the saturating condition is not detected, and aftematively to select a predetermined maximum value to form the first state metric when the saturating condition is detected; and

a comparator to compare saId first state metric to second state metric transmitted from a second adder, and to responsively, and to responsively select a minimum one of said state metrics.

2. The apparatus as in claim 1 further comprising:

an accumulator to store said selected minimum one of said first and second state metrics for subsequent path metric calculations.

3. The apparatus as in claim 2 wherein said predetermined maximum value is a maximum value that can be stared by said accumulator.

4. The apparatus as in claim 1 wherein said saturating logic comprises;

a multiplexer to select between said predetermined maximum value and said first path metric value, wherein said value of said MSB operates as selection logic to control said multiplexer.

6. The apparatus as in claim 2 further comprising:

a plurality of additional comparators to compare state metric values and select a minimum for a plurality of additional accumulators.

7. The apparatus as in claim 6 wherein the total number of accumulators is equal to a Viterbl trellis depth.

8. The apparatus as in claim 6 wherein the total number of accumulators is equal to 64.

5. The apparatus as in claim I wherein said predetermined maximum value is 7h7f.

9. A decoding method comprising:

adding a first branch metric value to a previous path metric value to generate a first path metric value;

detecting a saturating condition when a most significant bit (“

MSB”

) of said first path metric value is a specified value;

selecting the first path metric value as a first state metric when the saturating condition is not detected, end alternatively selecting a predetermined maximum value as the first state metric when the saturating condition is detected;

comparing said first state metric with a second state metric transmitted from a second adder; and

selecting a minimum one of said state metrics.

10. The method as in claim 9 further comprising:

storing said selected minimum one of said state metrics for subsequent path metric calculations.

11. The method as in claim 10 wherein said predetermined maximum value is a maximum value that can be stored by said accumulator.

12. The method as in claim 10 further comprising:

comparing state metric values and selecting a minimum for a plurality of additional accumulators.

13. The method as in claim 12 wherein the total number of accumulators Is equal to a Viterbi trellis depth.

14. The method as In claim 12 wherein the total number of accumulators is equal to 64.

15. The method as in claim 9 wherein selecting comprises:

configuring a multiplexer to select between said predetermined maximum value and said first path metric value, wherein said value of said MSB operates as selection logic to control said multiplexer.

16. The method as in claim 9 wherein said predetermined maximum value is 7h7f.

17. An integrated circuit (IC), comprising:

a first adder to add a first branch metric value to a previous path metric value to generate a first path metric value;

saturating logic to detect a saturating condition when a most significant bit (“

MSB”

) of said first path metric value is a specified value the saturating logic arranged to select the first path metric value, to form a first state metric when the saturating condition is riot detected, and alternatively to select a predetermined maximum value to form the first state metric when the saturating condition is detected; and

a comparator to compare said first state metric a second state metric transmitted from a second adder, and to responsively select a minimum one of said state metrics.

18. The integrated circuit as in claim 17 wherein said IC further comprises:

an accumulator to store said selected minimum one of said first and second state metrics for subsequent path metric calculations.

19. The integrated circuit as in claim 18 wherein said predetermined maximum value is a maximum value that can be stored by said accumulator.

20. Integrated circuit as in claim 17 wherein said saturating logic comprises:

a multiplexer to select between said predetermined maximum value and said first path metric value, wherein said value of said MSB operates as selection logic to control said multiplexer.

21. The integrated circuit as in claim 17 wherein said predetermined maximum value is 7h7.

22. The integrated circuit as in claim 17 further comprising:

a plurality of additional comparators to compare state metric values and select a minimum for a plurality of additional accumulators.

23. The integrated circuit as in claim 22 wherein the total number of accumulators fe equal to a Viterbi trellis depth.

24. The Integrated circuit as in claim 22 wherein the total number of accumulators is equal to 64.

25. A method for use in a digital decoder comprising the steps of:

determining a branch metric distance value;

monitoring a path metric accumulator value;

responsive to the path metric accumulator value reaching a first predetermined value, normalizing the path metric accumulator value by;

selecting a normalization quantity;

adding the selected normalization quantity to the branch metric distance value to form a sum; and

inputting the sum to the path metric accumulator, thereby adding the selected normalization quantity to the path metric accumulator value to normalize it.

26. A method according to claim 25 wherein:

said monitoring Is conducted over multiple path metric accumulator values; and

said normalizing step is triggered only when all of the monitored path metric accumulator values exceed the first predetermined value.

27. A method according to claim 26 wherein selecting the normalization quantity includes selecting one among a plurality of predetermined normalization quantities.

28. A method for use in a digital decoder comprising the steps of:

monitoring bit settings in each of a plurality of path metric accumulators, each accumulator providing a respective path metric accumulator value during a decoding operation;

detecting when all of the path metric accumulator values reaches at least a first predetermined value; and

responsive to all of the path metric accumulator values reaching at least the first predetermined value, selecting a normalization value and adding the selected normalization value to each of the path metric accumulators to normalize the accumulators.

29. A method according to claim 28 wherein the normalization value is selected from at least two predetermined normalization values.

30. A method according to claim 28 wherein said adding the selected normalization value comprises adding the selected normalization value to a branch metric value, and then updating the path metric accumulator with a sum of the branch metric value plus the selected normalization value.

31. A method according to claim 30 wherein selecting the normalization value includes selecting a negative normalization value Sc as to reduce the path metric accumulator value.

32. A method according to claim 28 wherein selecting the normalization value is based on the current bit settings of at least two MSB'"'"'s of the accumulator value.

33. A method according to claim 28 wherein selecting the normalization value includes selecting a negative normalization value having a magnitude equal to 2^N where N is a bit position of a most significant bit of the accumulator that is sat.

34. An add compare-select (ACS) circuit for use in a digital decoder apparatus comprising:

a first adder for adding a first branch metric value to a first path metric value to form a first sum;

saturation logic for detecting a saturation condition in the first adder;

a first multiplexer responsive to the saturation detecting logic for selecting either the first sum or a predetermined saturation value as a first state metric output;

a second adder for adding a second branch metric value to a second path metric value to form a second sum;

second saturation logic for detecting a saturation condition in the second adder;

a second multiplexer responsive to be second saturation detecting logic for selecting either the second sum or a predetermined saturation value as a second state metric output; and

a comparator for comparing the first and second state metric outputs.

35. An add-compare-select (ACS) circuit according to claim 34 wherein the saturation value is selected as maximum output value of the first adder.