Method and system for performing crosstalk analysis

• US 7,073,140 B1
• Filed: 08/29/2003
• Issued: 07/04/2006
• Est. Priority Date: 08/30/2002
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Zhao, Hong, Li, Jun, Chiu, Hsien-Yen, Spyrou, Athanasius
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): Bowers, Brandon
• Application Number:
  US10/651,617
• Time in Patent Office: 1,040 Days
• Field of Search: 716/4, 716/6, 716/5
• US Class Current: 716/115
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

Disclosed is an improved approach for performing crosstalk and signal integrity analysis in which multiple variables are taken into account when analyzing the effects of on-chip crosstalk, such as for example coupled wire length, ration of coupling capacitance, and aggressor and victim driver types. Rather than performing a full-chip simulation, the potential crosstalk effects can be pre-characterized by performing simulation/modeling over specific net portions by systematically changing the values of these multiple variables. A set of patterns characterized from the variables are formed from the modeling. During the analysis process, the IC design is checked of the presence of the patterns, from which is produced the expected delay impact for crosstalk in the design.

Claims

1. A method of performing crosstalk analysis for the design of an integrated circuit, comprising:

generating a set of multi-variable patterns corresponding to one or more configurations of IC components;

determining a delay impact of cross-talk for each of the multiple-variable patterns;

analyzing an IC design to determine whether any of the multi-variable patterns are present in the IC design; and

determining a performance effect on the IC design based upon the delay impacts respectively associated with the multi-variable patterns that are present in the IC design, wherein device-level simulation is performed to generate the set of multi-variable patterns and delay impact is fitted using the following fitting parameters;

D=C*L+C²*L+C*L²+C²*L²+(C*L+C²*L+C*L²+C²*L²)*Ax+(C*L+C²*L+C*L²+C²*L²)*Ax²

where C is coupling Cap ratio, L is coupling wire length (mm), and Ax is Aggressor driver size.

2. The method of claim 1 in which approximately or at least 192 simulations per delay transition edge are performed.

3. The method of claim 1 in which delay impact is evaluated against one or more of the variables to determine the performance effect of the IC design.

4. The method of claim 3 in which asymptotic delay uncertainty is tracked as a function of coupled wire length against driver-normalized delay.

5. The method of claim 1 in which HSPICE is employed for the simulation.

6. The method of claim 1 in which delay uncertainty is bounded with worst-case analysis.

7. The method of claim 1 in which D is generated over different victim driver types.

8. The method of claim 1 in which the entire IC design is analyzed for the existence of the multi-variable patterns.

9. The method of claim 1 in which only specified portions of the IC design are analyzed for the existence of the multi-variable patterns.

10. The method of claim 9 in which only wires having a given location, length, or specified characteristic are analyzed for the existence of the patterns.

11. The method of claim 1 in which delay impact is determined based upon numerical models for delay developed from characterizing a set of IC components.

12. The method of claim 1 further comprising:

modifying the IC design if excessive adverse performance effects are identified.

13. The method of claim 12 in which a replace or insert methodology is applied to modify the IC design.

14. The method of claim 13 in which the replace or insert methodology comprises adding buffers, modifying driver strengths, and/or enhancing grid spacing.

15. The method of claim 1 in which the multi-variable patterns comprise one or more of the following variable types:

wirelength values, aggressor driver type values, victim driver type values, and ratio of coupling capacitance values.

16. A system of performing crosstalk analysis for the design of an integrated circuit, comprising:

means for generating a set of multi-variable patterns corresponding to one or more configurations of IC components;

means for determining a delay impact of crosstalk for each of the multiple-variable patterns;

means for analyzing an IC design to determine whether any of the multi-variable patterns are present in the IC design; and

means for determining a performance effect on the IC design based upon the delay impacts respectively associated with the multi-variable patterns that are present in the IC design, wherein device-level simulation is performed to generate the set of multi-variable patterns and delay impact is fitted using the following fitting parameters;

D=C*L+C²*L+C*L²+C²*L²+(C*L+C²*L+C*L²+C²*L²)*Ax+(C*L+C²*L+C*L²+C²*L²)*Ax²

where C is coupling Cap ratio, L is coupling wire length (mm), and Ax is Aggressor driver size.

17. The system of claim 16 in which the means for generating is configured to perform approximately or at least 192 simulations per delay transition edge.

18. The system of claim 16 in which the means for determining is configured to evaluate delay impact against one or more of the variable to determine the performance effect on the IC design.

19. The system of claim 16 in which the means for generating is configured to employ HSPICE for the simulation.

20. The system of claim 16 in which the means for analyzing is configured to analyze the entire IC design for the existence of the multi-variable patterns.

21. The system of claim 16 in which the means for analyzing is configured to analyze only specified portions of the IC design for the existence of the multi-variable patterns.

22. The system of claim 16 further comprising:

means for modifying the IC design if excessive adverse performance effects are identified.

23. The system of claim 16 in which the multi-variable patterns comprise one or more of the following variable types:

wirelength values, aggressor driver type values, victim driver type values, and ratio of coupling capacitance values.

24. A computer program product comprising a computer usable medium having executable code to execute a process for performing crosstalk analysis for the design of an integrated circuit, the process comprising:

generating a set of multi-variable patterns corresponding to one or more configurations of IC components;

determining a delay impact of cross-talk for each of the multiple-variable patterns;

analyzing an IC design to determine whether any of the multi-variable patterns in the set of multi-variable patterns are present in the IC design; and

determining a performance effect on the IC design based upon the delay impacts respectively associated with the multi-variable patterns that are present in the IC design, wherein device-level simulation is performed to generate the set of multi-variable patterns and delay impact is fitted using the following fitting parameters;

D=C*L+C²*L+C*L²+C²*L²+(C*L+C²*L+C*L²+C²*L²)*Ax+(C*L+C²*L+C*L²+C²*L²)*Ax²

where C is coupling Cap ratio, L is coupling wire length (mm), and Ax is Aggressor driver size.

25. The computer program product of claim 24 in which approximately or at least 192 simulations per delay transition edge are performed.

26. The computer program product of claim 24 in which delay impact is evaluated against one or more of the variables to determine the performance effect on the IC design.

27. The computer program product of claim 26 in which asymptotic delay uncertainty is tracked as a function of coupled wire length against driver-normalized delay.

28. The computer program product of claim 24 in which HSPICE is employed for the simulation.

29. The computer program product of claim 24 in which delay uncertainty is bounded with worst-case analysis.

30. The computer program product of claim 24 in which the entire IC design is analyzed for the existence of the multi-variable patterns.

31. The computer program product of claim 24 in which only specified portions of the IC design are analyzed for the existence of the multi-variable patterns.

32. The computer program product of claim 24 in which the multi-variable patterns comprise one or more of the following variable types:

wirelength values, aggressor driver type values, victim driver type values, and ratio of coupling capacitance values.

33. A method for performing crosstalk analysis for the design of an integrated circuit, comprising:

characterizing a set of IC components based upon wirelength values, aggressor driver type values, victim driver type values, and ratio of coupling capacitance values;

identifying a set of patterns based upon the wirelength values, the aggressor driver type values, the victim driver type values, and the ratio of coupling capacitance values;

analyzing an IC design to identify the existence of any patterns from the set of patterns; and

determining delay impact of crosstalk based upon identifying the existence of the patterns, wherein delay impact is fitted using the following fitting parameters;

D=C*L+C²*L+C*L²+C²*L²+(C*L+C²*L+C*L²+C²*L²)*Ax+(C*L+C²*L+C*L²+C²*L²)*Ax²

where C is coupling Cap ratio, L is coupling wire length (mm), and Ax is Aggressor driver size.

34. The method of claim 33 in which device-level simulation is performed to characterize the set of IC components.

35. The method of claim 33 in which delay uncertainty is bounded with worst-case analysis.

36. The method of claim 33 in which the entire IC design is analyzed for the existence of the patterns.

37. The method of claim 33 in which only specified portions of the IC design are analyzed for the existence of the patterns.

38. The method of claim 37 in which only wires having a given location, length, or specified characteristic are analyzed for the existence of the patterns.

39. The method of claim 33 in which delay impact is determined based upon numerical models for delay developed from characterizing the set of IC components.

40. The method of claim 33 further comprising:

modifying the IC design if excessive adverse performance effects are identified.

41. A system for performing crosstalk analysis for the design of an integrated circuit, comprising:

means for characterizing a set of IC components based upon wirelength values, aggressor driver type values, victim driver type values, and ratio of coupling capacitance values;

means for identifying a set of patterns based upon the wirelength values, the aggressor driver type values, the victim driver type values, and the ratio of coupling capacitance values;

means for analyzing an IC design to identify the existence of any patterns from the set of patterns; and

means for determining delay impact of crosstalk based upon identifying the existence of the patterns, wherein delay impact is fitted using the following fitting parameters;

D=C*L+C²*L+C*L²+C²*L²+(C*L+C²*L+C*L²+C²*L²)*Ax+(C*L+C²*L+C*L²+C²*L²)*Ax²

where C is coupling Cap ratio, L is coupling wire length (mm), and Ax is Aggressor driver size.

42. The system of claim 41 in which device-level simulation is performed to characterize the set of IC components.

43. The system of claim 41 in which delay uncertainty is bounded with worst-case analysis.

44. The system of claim 41 in which the entire IC design is analyzed for the existence of the patterns.

45. The system of claim 41 in which only specified portions of the IC design are analyzed for the existence of the patterns.

46. The system of claim 41 in which delay impact is determined based upon numerical models for delay developed from characterizing the set of IC components.

47. The system of claim 41 further comprising:

means for modifying the IC design if excessive adverse performance effects are identified.