Automated system for designing and developing field programmable gate arrays

• US 7,073,158 B2
• Filed: 05/19/2003
• Issued: 07/04/2006
• Est. Priority Date: 05/17/2002
• Status: Expired due to Fees

• Current Assignee: Pixel Velocity Incorporated
• Original Assignee: Pixel Velocity Incorporated
• Inventors: McCubbrey, David L.
• Primary Examiner(s): DO, THUAN V
• Application Number:
  US10/441,581
• Publication Number:
  US 20040060032A1
• Time in Patent Office: 1,142 Days
• Field of Search: 716/16, 716/17, 716/1, 716/18
• US Class Current: 716/104
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 8/456 Parallelism detection
• CPC Class Codes: H05K 1/144 Stacked arrangements of planar printed circuit boards

Abstract

An automated system and method for programming field programmable gate arrays (FPGAs) is disclosed for implementing user-defined algorithms specified in a high level language. The system is particularly suited for use with image processing algorithms and can speed up the process of implementing and testing a fully written high-level user-defined algorithm to a matter of a few minutes, rather than the days, weeks or even months presently required using conventional software tools. The automated system includes an analyzer module and a mapper module. The analyzer determines what logic components are required and their interrelationships, and observes the relative timing between the required components and their partial products. It also ascertains when signal delays are required between selected components. The mapper module utilizes the output from the analyzer module and determines where the required logic components must be placed on a given target FPGA in order to reliably route, without interference, the required interconnections between various components and I/O. The mapper includes means for evaluating alternative interconnection routes between logic components within the target FPGA, and means for producing an optimized placement and routing of the logic components and interconnections on the target FPGA. The mapper also generates a low level command listing as a source file that serves as an input file for a conventional low-level FPGA programming tool. From that input file, the tool is able to generate a hardware gate-programming bitstream to be directed to the target FPGA, thereby programming the FPGA with the user-defined algorithm.

Claims

1. A method for programming a field programmable gate array (FPGA) comprising the following steps:

accepting a user-defined algorithm specified in a source code of a high level language and designed to process data vectors with one, two, or more dimensions;

analyzing the user-defined algorithm, including identifying the vector processing operations of the source code;

mapping the vector processing operations onto logic components of an FPGA; and

programming the FPGA with the user-defined algorithm based on the mapping of the logic components.

2. The method of claim 1, wherein the accepting of the user-defined algorithm includes accepting a user-defined algorithm specified in a high level language that is operable to specify vectors at the source code level through object types.

3. The method of claim 2, wherein the accepting of the user-defined algorithm includes accepting a user-defined algorithm specified in C++.

4. The method of claim 1, wherein the identifying of the vector processing operations includes parsing the source code.

5. The method of claim 4, wherein the analyzing of the user-defined algorithm includes determining the relative timing between the vector processing operations.

6. The method of claim 5, wherein the analyzing of the user-defined algorithm includes providing an operation dataflow graph that indicates the overall flow of vector processing results between vector operations.

7. The method of claim 1, wherein the analyzing of the user-defined algorithm includes identifying the type of operators and the vector input operands of the vector operations.

8. The method of claim 7, wherein the analyzing of the user-defined algorithm includes identifying the orders and dependencies of the vector operations.

9. The method of claim 1, further comprising:

providing a library of predefined functions, including first group of image processing functions, a second group of arithmetic functions, and third group of Boolean functions.

10. The method of claim 9, further comprising:

determining a first rule set that represents constraints associated with the FPGA and with at least some of the predefined functions in the library, wherein the analyzing of the user-defined algorithm includes accessing the first rule set.

11. The method of claim 10, further comprising:

determining a second rule set that represents constraints associated with the FPGA and with at least some of the predefined functions in the library, wherein the mapping of the logic components includes accessing the second rule set.

12. The method of claim 1, wherein the mapping of the vector processing operators onto FPGA logic components includes evaluating alternative component placement and interconnection routes between the logic components.

13. The method of claim 12, wherein the mapping of the vector processing operators onto FPGA logic components includes producing an optimized placement and interconnection routing of the logic components on the FPGA, based on the evaluation of alternative placement and interconnection routes.

14. The method of claim 13, wherein the mapping of the vector processing operators includes producing a generally serpentine vector flow path on the FPGA.

15. The method of claim 14, wherein the mapping of the vector processing operators includes instantiating substantially only logic components called out by the source code.

16. The method of claim 1, further comprising accepting a user selection for an architecture for the FPGA.

17. The method of claim 16, wherein the accepting of the user selection for an architecture for the FPGA includes accepting a user selection from the group including a parallel array processor, a raster sub-array processor, a pipeline raster sub-array processor, and a multi-pipeline raster sub-array processor.

18. The method of claim 1, wherein the programming of the FPGA includes generating a low level logic description and logic component placement listing.

19. The method of claim 18, wherein generating a low level logic description and logic component placement listing includes generating an input file for a low level conventional FPGA programming tool.

20. The method of claim 1, wherein the programming of the FPGA includes generating a hardware gate programming bitstream to be directed to the FPGA.