Silicon carbide power devices with self-aligned source and well regions and methods of fabricating same
First Claim
1. A method of fabricating a silicon carbide power device comprising:
- successively patterning a single mask layer to provide a first window for formation of a source region of a first conductivity type and a buried silicon carbide region of a second conductivity type opposite the first conductivity type and a second window for formation of a second conductivity type well region in a first conductivity type silicon carbide layer.
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Accused Products
Abstract
Silicon carbide semiconductor devices and methods of fabricating silicon carbide semiconductor devices are provided by successively etching a mask layer to provide windows for formation of a source region or a first conductivity type, a buried silicon carbide region of a second conductivity type opposite to the first conductivity type and a second conductivity type well region in a first conductivity type silicon carbide layer. The source region and the buried silicon carbide region are formed utilizing a first window of the mask layer. Then, the well region is formed utilizing a second window of the mask layer, the second window being provided by a subsequent etch of the mask layer having the first window.
142 Citations
17 Claims
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1. A method of fabricating a silicon carbide power device comprising:
successively patterning a single mask layer to provide a first window for formation of a source region of a first conductivity type and a buried silicon carbide region of a second conductivity type opposite the first conductivity type and a second window for formation of a second conductivity type well region in a first conductivity type silicon carbide layer. - View Dependent Claims (2, 3)
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4. A method of fabricating a silicon carbide power device comprising:
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successively patterning a mask layer to provide windows for formation of a source region of a first conductivity type, a buried silicon carbide region of a second conductivity type opposite the first conductivity type and a second conductivity type well region in a first conductivity type silicon carbide layer;
wherein the first conductivity type is n-type silicon carbide and the second conductivity type is p-type silicon carbide and wherein the buried silicon carbide region comprises a buried p-type silicon carbide region and the well region comprises a p-well region; and
wherein successively patterning a mask layer, forming the source region and the buried p-type silicon carbide region and forming the p-well region comprise;
forming the mask layer on a first surface of the first n-type silicon carbide layer;
patterning the mask layer to provide a first implantation mask, the first implantation mask having at least one window corresponding to the source region of the silicon carbide power device;
thenimplanting n-type dopants in the first n-type silicon carbide layer utilizing the first implantation mask having the at least one window to provide an n-type source region, the n-type source region extending to the first surface of the first n-type silicon carbide layer and having a higher carrier concentration than the first n-type silicon carbide layer;
implanting p-type dopants in the first n-type silicon carbide layer utilizing the first implantation mask having the at least one window to provide the buried p-type region adjacent the n-type source region, the buried p-type region being disposed at a depth in the first n-type silicon carbide layer greater than a depth of the n-type source region;
thenetching the first implantation mask to provide a second implantation mask, the second implantation mask having at least one window corresponding to the p-well region and corresponding to the at least one window of the first implantation mask widened by the etch; and
thenimplanting p-type dopants in the first n-type silicon carbide layer utilizing the second implantation mask to provide the p-well region, the p-well region extending to the p-type buried region.
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5. A method of fabricating a silicon carbide power device comprising:
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successively patterning a mask layer to provide a first window for formation of a source region of a first conductivity type and buried silicon carbide region of a second conductivity type opposite the first conductivity type and a second window for formation of a second conductivity type well region in a first conductivity type silicon carbide layer;
wherein the first conductivity type is n-type silicon carbide and the second conductivity type is p-type silicon carbide and wherein the buried silicon carbide region comprises a buried p-type silicon carbide region and the well region comprises a p-well region; and
wherein successively patterning a mask layer to provide windows for formation of a source region, a buried p-type silicon carbide region and a p-well region comprises successively patterning a mask layer to provide windows for formation of a source region, a buried p-type silicon carbide region, a p-well region and a threshold adjustment region in a first n-type silicon carbide layer, the method further comprising forming the threshold adjustment region utilizing a third window of the mask layer, the third window being provided by a subsequent etch of the mask layer having the second window.
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6. A method of fabricating a silicon carbide power device comprising:
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successively patterning a mask layer to provide windows for formation of a source region of a first conductivity type, a buried silicon carbide region of a second conductivity type opposite the first conductivity type and a second conductivity type well region in a first conductivity type silicon carbide layer;
wherein the first conductivity type is n-type silicon carbide and the second conductivity type is p-type silicon carbide and wherein the buried silicon carbide region comprises a buried p-type silicon carbide region and the well region comprises a p-well region; and
wherein successively patterning a mask layer, forming the source region and the buried p-type silicon carbide region and forming the p-well region comprise;
forming the mask layer on a first n-type silicon carbide layer;
patterning the mask layer to provide a first implantation mask, the first implantation mask having at least one window corresponding to the source region of the silicon carbide power device;
thenimplanting n-type dopants in the first n-type silicon carbide layer utilizing the first implantation mask having the at least one window to provide an n-type source region, the n-type source region extending to a first surface of the first n-type silicon carbide layer and having a higher carrier concentration than the first n-type silicon carbide layer;
implanting p-type dopants in the first n-type silicon carbide layer utilizing the first implantation mask having the at least one window to provide the buried p-type region adjacent the n-type source region, the p-type dopants being implanted utilizing a higher implantation energy than an implant energy utilized to implant the n-type dopants in the first n-type silicon carbide layer utilizing the first implantation mask to provide an n-type source region;
thenetching the first implantation mask to provide a second implantation mask, the second implantation mask having at least one window corresponding to the p-well region and corresponding to the at least one window of the first implantation mask widened by the etch; and
thenimplanting p-type dopants in the first n-type silicon carbide layer utilizing the second implantation mask to provide the p-well region, the p-type dopants being implanted utilizing an implantation energy such that the p-well region extends to the p-type buried region. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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Specification