Method for making a semiconductor device having a high-k gate dielectric

• US 7,074,680 B2
• Filed: 09/07/2004
• Issued: 07/11/2006
• Est. Priority Date: 09/07/2004
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Chau, Robert S., Doczy, Mark L., Dewey, Gilbert, Kavalieros, Jack, Brask, Justin K., Metz, Matthew V., Datta, Suman, Kuhn, Markus, Pae, Sangwoo, Sherrill, Adrian B.
• Primary Examiner(s): Kebede, Brook
• Application Number:
  US10/935,784
• Publication Number:
  US 20060051880A1
• Time in Patent Office: 672 Days
• Field of Search: 438/142, 438/197, 438/199, 438/211, 438/216, 438/218, 438/240, 438/261, 438/263, 438/264, 438/585, 438591-594, 438/287, 257410-412, 257/310
• US Class Current: 438/287
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/02142 the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
• CPC Class Codes: H01L 21/02175 characterised by the metal H01L21/02197 takes precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/3144 on silicon
• CPC Class Codes: H01L 21/31691 with perovskite structure
• CPC Class Codes: H01L 28/56 the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Abstract

A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.

Claims

1. A method for making a semiconductor device comprising:

forming an oxide layer on a substrate, wherein the oxide layer comprises a silicon oxynitride layer that is less than about 15 angstroms thick;

forming a high-k dielectric layer on the oxide layer;

forming a capping layer on the high-k dielectric layer;

annealing the oxide layer, the high-k dielectric layer and the capping layer at a sufficient temperature and for a sufficient time to generate a gate dielectric with a graded dielectric constant; and

removing the capping layer.

2. The method of claim 1 wherein the high-k dielectric layer is less than about 40 angstroms thick, and comprises a material that is selected form the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

3. The method of claim 1 wherein the silicon oxynitride layer and the high-k dielectric layer are annealed at a temperature of at least about 800°

C. for at least about 30 seconds.

4. The method of claim 3 wherein the silicon oxynitride layer and the high-k dielectric layer are annealed at a temperature that is between about 800°

C. and about 1,100°

C. for between about 30 seconds and about 5 minutes.

5. The method of claim 1 wherein the capping layer is a barrier layer that comprises a metal nitride.

6. The method of claim 1 wherein the capping layer comprises a metal that is selected from the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, a metal carbide, ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide.

7. A method for making a semiconductor device comprising:

forming a silicon oxynitride layer on a substrate;

forming a high-k dielectric layer on the silicon oxynitride layer;

forming a capping layer on the high-k dielectric layer;

annealing the silicon oxynitride layer and the high-k dielectric layer at a temperature of at least about 800°

C. for at least about 30 seconds to generate a gate dielectric with a graded dielectric constant; and

removing the capping layer after annealing the silicon oxynitride layer and the high-k dielectric layer.

8. The method of claim 7 wherein:

the silicon oxynitride layer is less than about 15 angstroms thick; and

the high-k dielectric layer is less than about 40 angstroms thick, and comprises a material that is selected form the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

9. The method of claim 7 wherein the capping layer is a barrier layer that comprises titanium nitride.

10. The method of claim 7 wherein the capping layer comprises titanium nitride or silicon.

11. The method of claim 7 wherein the capping layer comprises a metal that is selected from the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, a metal carbide, ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide.

12. A method for making a semiconductor device comprising:

forming a silicon oxynitride layer on a substrate;

forming a high-k dielectric layer on said silicon oxynitride layer;

forming a sacrificial capping layer on said high-k dielectric layer; and

subsequent to forming said sacrificial capping layer, annealing said silicon oxynitride layer and said high-k dielectric layer at a sufficient temperature and for a sufficient time to generate a gate dielectric with a graded dielectric constant; and

removing said sacrificial capping layer.

13. The method of claim 12 wherein said high-k dielectric layer is less than about 40 angstroms thick and comprises a material that is selected form the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide and lead zinc niobate.

14. The method of claim 13 wherein said sacrificial capping layer comprises a metal that is selected from the group consisting of a metallic nitride, hafnium, zirconium, titanium, tantalum, aluminum, a metal carbide, ruthenium, palladium, platinum, cobalt, nickel and a conductive metal oxide.

15. The method of claim 12 wherein said gate dielectric with said graded dielectric constant comprises a bottom surface like said silicon oxynitride layer, a top surface like said high-k dielectric layer and a graded silicate in between.

16. The method of claim 12 wherein said sacrificial capping layer is removed by applying a wet etch process that is selective for said sacrificial capping layer over said gate dielectric with said graded dielectric constant.

17. A method for making a semiconductor device comprising:

forming a silicon oxynitride layer on a substrate; and

subsequent to forming said silicon oxynitride layer, forming a high-k dielectric layer on said silicon oxynitride layer; and

subsequent to forming said high-k dielectric layer, forming a capping layer on said high-k dielectric layer; and

subsequent to forming said capping layer, annealing said silicon oxynitride layer, said high-k dielectric layer and said capping layer at a sufficient temperature and for a sufficient time to generate a gate dielectric with a graded dielectric constant; and

subsequent to annealing said silicon oxynitride layer, said high-k dielectric layer and said capping layer, removing said capping layer.

18. The method of claim 17 wherein said gate dielectric with said graded dielectric constant comprises a bottom surface like said silicon oxynitride layer, a top surface like said high-k dielectric layer and a graded silicate in between.

19. The method of claim 17 wherein said capping layer is removed by applying a wet etch process that is selective for said capping layer over said gate dielectric with said graded dielectric constant.

20. The method of claim 17 wherein said silicon oxynitride layer, said high-k dielectric layer and said capping layer are annealed a temperature of at least about 800°

C. for at least about 30 seconds.