Poly-sealed silicide trench gate
First Claim
1. A power MOSFET comprising:
- a substrate comprising a first trench extending from a top surface of the substrate;
a source region, a channel region, and a drain region in the substrate and arranged vertically along at least a portion of a wall of the first trench;
an insulating layer lining the wall of the first trench; and
a gate structure comprising a metal/silicide region in the first trench and a silicon layer between the metal/silicide region and the insulating layer.
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Accused Products
Abstract
Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The gate bus trench and/or gate structures in the device trenches can contain a metal/silicide to reduce resistance, where polysilicon layers surround the metal/silicide to prevent metal atoms from penetrating the gate oxide in the device trenches. CMP process can remove excess polysilicon and metal and planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with processes forming self-aligned or conventional contacts in the active device region.
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Citations
15 Claims
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1. A power MOSFET comprising:
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a substrate comprising a first trench extending from a top surface of the substrate;
a source region, a channel region, and a drain region in the substrate and arranged vertically along at least a portion of a wall of the first trench;
an insulating layer lining the wall of the first trench; and
a gate structure comprising a metal/silicide region in the first trench and a silicon layer between the metal/silicide region and the insulating layer. - View Dependent Claims (2, 3, 4, 5)
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6. A method for fabricating a power MOSFET comprising:
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forming a first trench in a substrate;
forming an insulating layer on walls of the first trench;
depositing a first silicon layer that lines the first trench;
depositing a metal layer on the first silicon layer in the first trench;
depositing a second silicon layer on the metal layer so that the first and second silicon layers surround the metal layer; and
doping the substrate adjacent the first trench to form a source region, a channel region, and a drain region that are vertically aligned along a wall of the first trench. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15)
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Specification