Low on resistance power MOSFET with variably spaced trenches and offset contacts

• US 7,075,147 B2
• Filed: 06/08/2004
• Issued: 07/11/2006
• Est. Priority Date: 06/11/2003
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Cao, Jianjun
• Primary Examiner(s): Munson, Gene M.
• Application Number:
  US10/864,056
• Publication Number:
  US 20050006700A1
• Time in Patent Office: 763 Days
• Field of Search: 257329-331
• US Class Current: 257/331
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power semiconductor device of the trench variety in which the trenches follow a serpentine path.

Claims

1. A MOS-gated semiconductor power device comprising:

a semiconductor body having a first major surface and a second opposing major surface;

a base region of a first conductivity type formed in said semiconductor body below said first major surface;

a first trench and a second trench formed in said semiconductor body, said first trench being spaced from said second trench by a first semiconductor region and a second semiconductor region, said first region being wider than said second region, and including access to said base region;

a gate structure formed in each of said trenches;

a conductive region of a second conductivity type formed adjacent each of said trenches; and

an external contact in electrical contact with said conductive regions of said second conductivity type and said base region at said first region;

wherein said trenches follow a serpentine path, wherein said trenches advance along a common direction of advancement, and wherein said serpentine path is comprised of smooth curves that together form a sinusoidal pattern.

2. A MOS-gated semiconductor power device according to claim 1, wherein said trenches are mirror images of one another.

3. A MOS-gated semiconductor power device according to claim 1, wherein said conductive regions are source regions and said external contact is a source contact.

4. A MOS-gated semiconductor power device according to claim 1, further comprising low resistivity regions formed in said base region and in electrical contact with said external contact.

5. A MOS-gated semiconductor power device comprising:

a silicon body having a first major surface and a second opposing major surface, and including a substrate portion and an epitaxial portion formed over a major surface of said substrate portion;

a base region of a first conductivity type formed in said epitaxial portion below said first major surface of said silicon body;

a first trench and a second trench formed in said epitaxial portion, said first trench being spaced from said second trench by a first silicon region and a second silicon region, said first region being wider than said second region;

a gate structure formed in each of said trenches;

a conductive region of a second conductivity type formed adjacent each of said trenches; and

an external contact in electrical contact with said conductive regions of said second conductivity type and making electrical connection to said base region;

wherein said trenches follow a serpentine path, and wherein said serpentine path is generally sinusoidal and is comprised of smooth curves that alternately change direction.

6. A MOS-gated semiconductor power device according to claim 5, wherein said trenches are mirror images of one another.

7. A MOS-gated semiconductor power device according to claim 5, wherein said conductive regions are source regions and said external contact is a source contact.

8. A MOS-gated semiconductor power device according to claim 5, further comprising low resistivity regions formed in said base region in electrical contact with said external contact.

9. A MOS-gated semiconductor power device according to claim 5, further comprising another external contact in electrical contact with said substrate.

10. A MOS-gated semiconductor power device according to claim 9, wherein said external contact is a drain contact.