Apparatus and method for making a low capacitance artificial nanopore
First Claim
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1. An apparatus for the construction of one of a microscale and nanoscale device, comprising:
- a first region comprising a diaphragm, the diaphragm comprising a first insulator material, the diaphragm having a top surface and a bottom surface,a second region comprising a second insulator material laterally surrounding the first region and having an upper surface substantially flush with the bottom surface of the first region,a substrate region comprising semiconductor material supporting the first region, the semiconductor material comprising a rigid frame laterally surrounding the diaphragm, wherein the second region is positioned between a portion of the bottom surface of the first region and a portion of an upper surface of the substrate region,a substrate cavity region beneath the diaphragm,a third region comprising a third insulator material, the third region being disposed atop the diaphragm, the third region being substantially thicker than the diaphragm and having a third cavity therethrough exposing a portion of the top surface of the diaphragm, the exposed portion of the top surface of the diaphragm being suitable for fabrication of one of a microscale and a nanoscale device.
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Abstract
An apparatus and method for making a nanopore chip exhibiting low capacitance. The apparatus provides a thin diaphragm on a rigid semiconductor frame suitable for nanopore fabrication, the diaphragm having associated thicker insulator regions to reduce capacitance. Also disclosed is a method of making the apparatus.
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Citations
34 Claims
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1. An apparatus for the construction of one of a microscale and nanoscale device, comprising:
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a first region comprising a diaphragm, the diaphragm comprising a first insulator material, the diaphragm having a top surface and a bottom surface, a second region comprising a second insulator material laterally surrounding the first region and having an upper surface substantially flush with the bottom surface of the first region, a substrate region comprising semiconductor material supporting the first region, the semiconductor material comprising a rigid frame laterally surrounding the diaphragm, wherein the second region is positioned between a portion of the bottom surface of the first region and a portion of an upper surface of the substrate region, a substrate cavity region beneath the diaphragm, a third region comprising a third insulator material, the third region being disposed atop the diaphragm, the third region being substantially thicker than the diaphragm and having a third cavity therethrough exposing a portion of the top surface of the diaphragm, the exposed portion of the top surface of the diaphragm being suitable for fabrication of one of a microscale and a nanoscale device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. An apparatus for the construction of one of a microscale and nanoscale device, comprising:
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a first region comprising a diaphragm, the diaphragm comprising a first insulator material, the diaphragm having a top surface and a bottom surface, a second region comprising a second insulator material laterally surrounding the first region and having an upper surface substantially flush with the bottom surface of the first region, a substrate region comprising semiconductor material supporting the first region, the semiconductor material comprising a rigid frame laterally surrounding the diaphragm, wherein the second region is positioned between a portion of the bottom surface of the first region and a portion of an upper surface of the substrate region, a substrate cavity region beneath the diaphragm, a third region comprising a third insulator material, the third region being disposed atop the diaphragm, the third region being substantially thicker than the diaphragm and having a third cavity therethrough exposing a portion of the top surface of the diaphragm, the exposed portion of the top surface of the diaphragm being suitable for fabrication of one of a microscale and a nanoscale device, wherein the third insulator material provides for low-capacitance across the top surface of the diaphragm. - View Dependent Claims (28, 29, 30, 31)
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32. An apparatus for the construction of one of a microscale and nanoscale device, comprising:
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a first region comprising a diaphragm, the diaphragm comprising a first insulator material, the diaphragm having a top surface and a bottom surface, a second region comprising a second insulator material laterally surrounding the first region and having an upper surface substantially flush with the bottom surface of the first region, a substrate region comprising semiconductor material supporting the first region, the semiconductor material comprising a rigid frame laterally surrounding the diaphragm, wherein the second region is positioned between a portion of the bottom surface of the first region and a portion of an upper surface of the substrate region, a substrate cavity region beneath the diaphragm, a third region comprising a third insulator material, the third region being disposed atop the diaphragm, the third region being substantially thicker than the diaphragm and having a third cavity therethrough exposing a portion of the top surface of the diaphragm, the exposed portion of the top surface of the diaphragm being suitable for fabrication of one of a microscale and a nanoscale device, and a microfluidic lead, said lead being disposed at a location comprising one of beneath the third region, and atop the third region.
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33. An apparatus for the construction of one of a microscale and nanoscale device, comprising:
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a first region comprising a diaphragm, the diaphragm comprising a first insulator material, the diaphragm having a top surface and a bottom surface, a second region comprising a second insulator material laterally surrounding the first region and having an upper surface substantially flush with the bottom surface of the first region, a substrate region comprising semiconductor material supporting the first region, the semiconductor material comprising a rigid frame laterally surrounding the diaphragm, wherein the second region is positioned between a portion of the bottom surface of the first region and a portion of an upper surface of the substrate region, a substrate cavity region beneath the diaphragm, a third region comprising a third insulator material, the third region being disposed atop the diaphragm, the third region being substantially thicker than the diaphragm and having a third cavity therethrough exposing a portion of the top surface of the diaphragm, the exposed portion of the top surface of the diaphragm being suitable for fabrication of one of a microscale and a nanoscale device, and a fifth material, the fifth material comprising a bottom layer portion of the diaphragm.
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34. An apparatus for the construction of one of a microscale and nanoscale device, comprising:
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a first region comprising a diaphragm, the diaphragm comprising a first insulator material, the diaphragm having a top surface and a bottom surface, a second region comprising a second insulator material laterally surrounding the first region and having an upper surface substantially flush with the bottom surface of the first region, a substrate region comprising semiconductor material supporting the first region, the semiconductor material comprising a rigid frame laterally surrounding the diaphragm, wherein the second region is positioned between a portion of the bottom surface of the first region and a portion of an upper surface of the substrate region, a substrate cavity region beneath the diaphragm, a third region comprising a third insulator material, the third region being disposed atop the diaphragm, the third region being substantially thicker than the diaphragm and having a third cavity therethrough exposing a portion of the top surface of the diaphragm, the exposed portion of the top surface of the diaphragm being suitable for fabrication of one of a microscale and a nanoscale device, and a sixth region comprising a sixth insulator material disposed atop the substrate region.
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Specification