Frequency boosting circuit for high swing cascode biasing circuits

• US 7,075,361 B1
• Filed: 04/01/2005
• Issued: 07/11/2006
• Est. Priority Date: 02/27/2004
• Status: Expired due to Fees

• Current Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Aram, Farbod
• Primary Examiner(s): ZWEIZIG, JEFFERY SHAWN
• Application Number:
  US11/097,530
• Time in Patent Office: 466 Days
• Field of Search: 327/530, 327/534, 327/535, 327/537, 327/538, 327/540, 327/541, 327/542, 327/543, 327/551, 327/552, 327/558, 327/559
• US Class Current: 327/543
• CPC Class Codes: G05F 3/262 using field-effect transistors only

Abstract

A high swing cascode biasing circuit includes first through sixth transistors, each including first, second, and control terminals. The second terminals of the first, third and fifth transistors communicate with the first terminals of the second, fourth and sixth transistors. The first terminal of the first transistor communicates with the control terminals of the third and fifth transistors. The first terminal of the third transistor communicates with the control terminals of the fourth and sixth transistors. A resistance communicates between the first terminal of the first transistor and the control terminals of the first and second transistors. A first capacitance communicates between the control terminals of the first and second transistors and the second terminal of the fifth transistor and the first terminal of the sixth transistor. A second capacitance communicates between the second terminal of the fifth transistor and the first terminal of the sixth transistor.

Claims

1. A high swing cascode biasing circuit, comprising:

first, second, third, fourth, fifth, and sixth transistors, each with a first terminal, a second terminal, and a control terminal,

wherein said second terminals of said first, third and fifth transistors communicate with said first terminals of said second, fourth and sixth transistors, said first terminal of said first transistor communicates with said control terminals of said third and fifth transistors, and said first terminal of said third transistor communicates with said control terminals of said fourth and sixth transistors;

a resistance having a first end that communicates with said first terminal of said first transistor and a second end that communicates with said control terminals of said first and second transistors;

a first capacitance having a first end that communicates with said control terminals of said first and second transistors and a second end that communicates with said second terminal of said fifth transistor and said first terminal of said sixth transistor; and

a second capacitance having a first end that communicates with said second terminal of said fifth transistor and said first terminal of said sixth transistor.

2. The high swing cascode biasing circuit of claim 1 further comprising a third capacitance having a first end that communicates with said second terminal of said first transistor and a first terminal of said second transistor.

3. The high swing cascode biasing circuit of claim 1 wherein the high swing cascade biasing circuit is implemented in an Ahuja compensation circuit.

4. The high swing cascode biasing circuit of claim 1 wherein said first, second, third, fourth, fifth, and sixth transistors are metal-oxide semiconductor field-effect transistors (MOSFETs).

5. The high swing cascode biasing circuit of claim 1 wherein said resistance is one of a standard fixed-value resistor, a nonlinear variable resistor and a metal-oxide-semiconductor (MOS) resistor.

6. A high swing cascode biasing circuit, comprising:

a current biasing circuit including first, second, third and fourth transistors each including a control terminal and first and second terminals, wherein said second terminals of said first and third transistors communicate with said first terminals of said second and fourth transistors, said control terminal of said first transistor communicates with said control terminal of said second transistor, and said first terminal of said third transistor communicates with said control terminal of said fourth transistor;

a current mirror circuit that includes fifth and sixth transistors each including a control terminal and first and second terminals and a first capacitance having one end connected between said second terminal of said fifth transistor and said first terminal of said sixth transistor;

a resistance having one end that communicates with said first terminal of said first transistor and an opposite end that communicates with said control terminal of said first transistor; and

a second capacitance having one end that communicates with said control terminals of said first and second transistors and an opposite end that communicates with said one end of said first capacitance, wherein said control terminals of said fifth and sixth transistors communicate with said control terminals of said third and fourth transistors.

7. The high swing cascode biasing circuit of claim 6 further comprising a third capacitance having one end that communicates with said second terminal of said first transistor and said first terminal of said first capacitance.

8. The high swing cascode biasing circuit of claim 6 wherein the high swing cascade biasing circuit is implemented in an Ahuja compensation circuit.

9. The high swing cascode biasing circuit of claim 6 wherein said first, second, third and fourth transistors are metal-oxide semiconductor field-effect transistors (MOSFETs).

10. The high swing cascode biasing circuit of claim 6 wherein said resistance is one of a standard fixed-value resistor, a nonlinear variable resistor and a metal-oxide-semiconductor (MOS) resistor.