Methods, circuits, and applications using a resistor and a Schottky diode

• US 7,075,763 B2
• Filed: 10/31/2002
• Issued: 07/11/2006
• Est. Priority Date: 10/31/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Marr, Kenneth W.
• Primary Examiner(s): LEJA, RONALD W
• Application Number:
  US10/284,808
• Publication Number:
  US 20040085093A1
• Time in Patent Office: 1,349 Days
• Field of Search: 361/56, 361/111, 361/91.1, 361/91.6, 361/91.5, 257/355, 257/356, 257/357, 257/358, 257/474, 257/476, 257/477
• US Class Current: 361/56
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H03K 17/08142 in field-effect transistor switches
• CPC Class Codes: H03K 5/08 by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30

Abstract

A combination of a current limiting resistor and a clamping Schottky diode prevent substantial forward biasing of a pn junction associated with a pad in a snapback device during normal operation, but do not substantially affect triggering of the device during an unbiased electrostatic discharge event. Minority carrier injection from n+ devices is substantially reduced, and the circuit may also be used to clamp an oxide voltage in a thin oxide semiconductor device.

Claims

1. An integrated circuit for protecting an electrostatic discharge protection (ESD) device, comprising:

a resistor sharing a common support surface with the ESD device; and

a Schottky diode connected in series with the resistor and sharing a common support surface with the ESD device to prevent forward biasing of a pn junction of the ESD device.

2. The integrated circuit of claim 1, wherein the terminals of the integrated circuit are connected across a base to emitter junction of the ESD protection device.

3. The integrated circuit of claim 1, wherein the terminals of the integrated circuit are connected between ground and an input pad of the ESD device.

4. The integrated circuit of claim 1, wherein the resistor has a resistance configured to limit current through the Schottky diode during an ESD event.

5. The integrated circuit of claim 1, wherein the Schottky diode has an area configured to clamp a pad voltage to less than a source triggered snapback voltage for a pn diode of the ESD device.

6. The integrated circuit of claim 5, wherein the pad is an input pad.

7. The integrated circuit of claim 5, wherein the pad is an output pad.

8. The integrated circuit of claim 5, wherein the pad is an input/output pad.

9. An electrostatic discharge protection device, comprising:

a snapback device having a parasitic bipolar transistor; and

a protection circuit for the snapback device, wherein the protection circuit comprises;

a resistor; and

a Schottky diode, the resistor and the Schottky diode connected in series across a base emitter junction of the parasitic bipolar transistor.

10. The ESD protection device of claim 9, wherein a Schottky diode undershoot current is no less than an undershoot current of the base emitter junction for a given voltage.

11. An electrostatic discharge protection device, comprising:

a snapback device having a parasitic bipolar transistor; and

protection circuit for the snapback device, wherein the protection circuit is connected across the base to emitter junction of the snapback device.

12. The ESD protection device of claim 11, wherein the snapback device is a metal oxide semiconductor (MOS) device.

13. The ESD protection device of claim 11, wherein the snapback device is a shallow trench isolation (STI) device.

14. The ESD protection device of claim 11, wherein the snapback device is a local oxidation of silicon (LOCOS) device.

15. A processing system, comprising:

a processor; and

a memory coupled to the processor to store data provided by the processor and to provide data to the processor, the memory comprising;

an array of memory cells addressable by address circuitry and input output circuitry; and

an electrostatic discharge protection device for the input output circuitry, the ESD protection device comprising;

an ESD protective transistor; and

an ESD protection circuit to prevent forward biasing of a pn junction of the ESD transistor.

16. The processing system of claim 15, wherein the ESD protection circuit comprises:

a resistor; and

a Schottky diode connected in series with the resistor.

17. The processing system of claim 16, wherein the Schottky diode has an area configured to clamp an input pad voltage to less than a source triggered snapback voltage for an ESD parasitic transistor of the ESD device.

18. The processing system of claim 15, wherein the ESD protective transistor has a parasitic bipolar transistor, and wherein the ESD protection circuit is connected in parallel with the base to emitter junction of the parasitic bipolar transistor.

19. A processing system, comprising:

a processor; and

a memory coupled to the processor to store data provided by the processor and to provide data to the processor, the memory comprising;

an array of memory cells addressable by address circuitry;

input/output circuitry to receive data from the processor and to pass the data to the array; and

an electrostatic discharge (ESD) protection device connected to the input/output circuitry, the ESD device comprising;

an ESD protective transistor; and

an ESD protection circuit to prevent forward biasing of a pn junction of the ESD transistor.

20. The processing system of claim 19, wherein the memory is a static random access memory (SRAM).

21. The processing system of claim 20, wherein the ESD protection circuit comprises:

a resistor; and

a Schottky diode connected in series with the resistor.

22. A method of preventing substantial forward bias of a snapback transistor junction in a snapback device, comprising:

clamping the forward bias using a clamping circuit; and

limiting a current through the clamping circuit, wherein clamping the forward bias comprises connecting a Schottky diode across a base to emitter junction of the snapback device.

23. The method of claim 22, wherein limiting the current comprises connecting a resistor in series with the Schottky diode.

25. The method of claim 22, and further comprising:

configuring an area of the first Schottky diode to limit the oxide voltage to less than a maximum oxide voltage.

26. The method of claim 22, and further comprising:

configuring a resistance of the first resistor to limit the current during an ESD event.

24. A method of clamping an oxide voltage in a thin oxide device, comprising:

connecting a first Schottky diode clamp circuit across the oxide of the thin oxide device; and

limiting a first current through the clamp circuit using a first resistor connected in series with the Schottky diode.

27. The method of claim 24, wherein the first Schottky diode and the first resistor are connected between a pad and a supply voltage.

28. The method of claim 24, and further comprising:

connecting a second Schottky diode clamp circuit across the oxide of the thin oxide device; and

limiting a second current through the second clamp circuit using a second resistor connected in series with the second Schottky diode.

29. The method of claim 28, wherein the first Schottky diode and the first resistor are connected between a pad and a supply voltage, and wherein the second Schottky diode and the second resistor are connected between a pad and a ground voltage.

30. A method for protecting an electrostatic discharge device during an undershoot event, comprising:

suppressing minority carrier injection with a circuit, wherein suppressing minority carrier injection comprises connecting a Schottky diode and a resistor in series across a pn junction on the device.

31. A method of substantially preventing forward bias of a base emitter junction of a bipolar transistor in a snapback device, comprising:

connecting a Schottky diode and a resistor in series across the junction.