FeRAM and sense amplifier array having data bus pull-down sensing function and sensing method using the same

• US 7,075,845 B2
• Filed: 06/30/2004
• Issued: 07/11/2006
• Est. Priority Date: 12/04/2003
• Status: Expired due to Fees

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kang, Hee Bok
• Primary Examiner(s): Nguyen, Tuan T.
• Application Number:
  US10/879,319
• Publication Number:
  US 20050122813A1
• Time in Patent Office: 741 Days
• Field of Search: 365/207, 365/205, 365/189.11, 365/189.05
• US Class Current: 365/207
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A nonvolatile ferroelectric memory device features a data bus pull-down sensing function. The nonvolatile ferroelectric memory device having a data bus pull-down sensing function comprises a plurality of cell array blocks, a common data bus unit and a sense amplifier array unit. The sense amplifier array unit pulls down a voltage of the common data bus unit before read data are sensed to a predetermined level to improve transmission characteristics of cell data to a data bus. As a result, the data sensing speed is improved.

Claims

1. A sense amplifier array having a data bus pull-down sensing function for sensing data outputted through a data bus from a cell array having a hierarchical bit line architecture including main bit lines and sub bit lines, the sense amplifier array comprising:

a bus pull-up unit for pulling up the data bus in a precharge mode;

a bus pull-down unit for pulling down a voltage of the pulled-up data bus to a predetermined level before data are sensed;

a sense amplifier unit for sensing a voltage of the data bus depending on a previously set sensing detection threshold voltage;

a lock switch unit for selectively transmitting data sensed in the sense amplifier unit in response to a lock signal;

a data latch unit for storing data transmitted through the lock switch unit;

a data-out regulating unit for transmitting data stored in the data latch unit to a data buffer for external output; and

a write switch unit for selectively transmitting data of the data-out regulating unit to the data bus for data restoration.

2. The sense amplifier array according to claim 1, wherein the bus pull-down unit comprises:

a pull-down regulating unit for activating a pull-down signal when a voltage of the data bus is higher than the predetermined level while a bus pull-down control signal is activated; and

a pull-down level regulating unit for pulling down a voltage of the data bus to the predetermined level while the pull-down signal is activated.

3. The sense amplifier array according to claim 2, wherein the pull-down level regulating unit comprises:

a first switch unit for activating the pull-down level regulating unit when the bus pull-down control signal is activated; and

a second switch unit for regulating time required until the data bus is pulled down to the predetermined level in response to the pull-down signal when the pull-down level regulating unit is activated.

4. The sense amplifier array according to claim 3, wherein the second switch unit is connected between the data bus and the first switch unit, and at least one or more of switch devices connected in parallel and selectively turned on/off in response to the pull-down signal.

5. The sense amplifier array according to claim 3, wherein the second switch unit comprises:

a third switch unit connected between the data bus and the first switch unit, and selectively turned on/off in response to the pull-down signal;

at least one or more of fourth switch units selectively connected in parallel to the third switch unit, and selectively turned on/off in response to the pull-down signal; and

a regulating switch unit corresponding one by one to the fourth switch units, and for selectively connecting the third switch unit to the fourth switch units in parallel.

6. A nonvolatile ferroelectric memory device having a data bus pull-down sensing function, comprising:

a plurality of cell array blocks each comprising a cell array having a hierarchical bit line architecture and storing cell data;

a common data bus shared by the plurality of cell array blocks, and for transmitting read data and write data; and

a sense amplifier array unit connected to the common data bus, and for sensing the read data transmitted from the common data bus and transmitting the write data to the common data bus,

wherein the sense amplifier array unit pulls down a voltage of the common data bus to a predetermined level before the read data are sensed.

7. The nonvolatile ferroelectric memory device according to claim 6, wherein the sense amplifier array unit comprises:

a bus pull-up unit for pulling up the common data bus in a precharge mode;

a bus pull-down unit for pulling down a voltage of the pulled-up common data bus to a predetermined level before the read data are sensed;

a sense amplifier unit for sensing a voltage of the data bus depending on a previously set sensing detection threshold voltage;

a lock switch unit for selectively transmitting data sensed in the sense amplifier unit in response to a lock signal;

a data latch unit for storing data transmitted through the lock switch unit;

a data-in regulating unit for transmitting the write data received from a data buffer to the data latch unit in a write mode;

a data-out regulating unit for transmitting data stored in the data latch unit to the common data bus or the common data bus and the data buffer depending on the operation mode; and

a write switch unit for transmitting data of the data-out regulating unit to the common data bus for data restoration.

8. The nonvolatile ferroelectric memory device according to claim 7, wherein the bus pull-down unit comprises:

a pull-down regulating unit for activating a pull-down signal when a voltage of the data bus is higher than the predetermined level while a bus pull-down control signal is activated; and

a pull-down level regulating unit for pulling down a voltage of the data bus to the predetermined level while the pull-down signal is activated.

9. The nonvolatile ferroelectric memory device according to claim 8, wherein the pull-down level regulating unit comprises:

a first switch unit for activating the pull-down level regulating unit when the bus pull-down control signal is activated; and

a second switch unit for regulating time required until the data bus is pulled down to the predetermined level in response to the pull-down signal when the pull-down level regulating unit is activated.

10. The nonvolatile ferroelectric memory device according to claim 9, wherein the second switch unit is connected between the data bus and the first switch unit, and comprises at least one or more of switch devices connected in parallel and selectively turned on/off in response to the pull-down signal.

11. The nonvolatile ferroelectric memory device according to claim 9, wherein the second switch unit comprises:

a third switch unit connected between the common data bus and the first switch unit, and selectively turned on/off in response to the pull-down signal;

at least one or more of fourth switch units selectively connected in parallel to the third switch unit, and selectively turned on/off in response to the pull-down signal; and

a regulating switch unit corresponding one by one to the fourth switch units, and for selectively connecting the third switch unit to the fourth switch units in parallel.

12. A data sensing method using a data bus pull-down function in a memory device comprising a plurality of cell array blocks each comprising cell arrays having a hierarchical bit line architecture and a common data bus shared by the cell array blocks, the method comprising the steps of:

pulling up the main bit line and the common data bus in a precharge mode;

pulling down the pulled-up common data bus to a predetermined level before data are sensed; and

inducing voltage change of the common data bus by a sensing voltage induced to the main bit line while the common data bus is pulled down to the predetermined level, and sensing the voltage change of the common data bus by using a previously set sensing detection threshold voltage.

13. The method according to claim 12, wherein the predetermined level is the sensing detection threshold voltage.