Distributed write data drivers for burst access memories

• US 7,075,857 B2
• Filed: 08/29/2002
• Issued: 07/11/2006
• Est. Priority Date: 12/23/1994
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy A., Merritt, Todd A.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US10/232,978
• Publication Number:
  US 20030063502A1
• Time in Patent Office: 1,412 Days
• Field of Search: 365/185.01, 365/189.01, 365/189.05, 365/230.01, 365/230.06, 365/233, 365/233.5, 365/238.5, 365/230.08
• US Class Current: 365/233.5
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1024 Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
• CPC Class Codes: G11C 7/1027 Static column decode serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled bit line addresses
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies. Local logic gates near array sense amplifiers are used to control write data drivers to provide for maximum write times without crossing current during input/output line equilibration periods. By gating global write enable signals with global equilibrate signals locally at data sense amp locations, local write cycle control signals are provided which are valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory devices. For nonburst mode memory devices such as EDO and Fast Page Mode, the write function may begin immediately following the end of the equilibration cycle to provide a maximum write time without interfering with the address setup time of the next access cycle.

Claims

1. A method of operating a system including a memory device having a standard DRAM pinout, the method comprising:

inputting a single address to the memory device;

inputting a control signal to the memory device; and

sequentially outputting two or more bytes from the memory device based on the single address input and two or more corresponding transitions of the control signal.

2. The method of claim 1, wherein the recited steps are initiated in the recited order.

3. The method of claim 1, wherein the memory device is a burst extended data out dynamic random access memory device.

4. A method of operating a system including a memory device having a standard DRAM pinout, the method comprising:

inputting a single address to the memory device;

inputting a control signal to the memory device; and

sequentially outputting two or more bytes from the memory device based on the single address input and two or more corresponding transitions of the control signal, wherein outputting two or more bytes from memory device comprises;

initiating output of a first of the two or more bytes on a transition of the control signal; and

continuing to output the first of the two or more bytes for a select high or low interval of the control signal after the transition to allow additional time for the system to latch the first byte.

5. The method of claim 4, wherein the recited steps are initiated in the recited order.

6. The method of claim 4, wherein the memory device is a burst extended data out dynamic random access memory device.

7. A method of operating a system including a memory device having a standard DRAM pinout, the method comprising:

inputting a single address to the memory device;

inputting a control signal to the memory device;

sequentially outputting two or more bytes from the memory device based on the single address input and two or more corresponding transitions of the control signal;

changing a count of an address counter within the memory device in response to transitions in the control signal; and

wherein sequentially outputting two or more bytes from the memory device is based on the single address and the count of the address counter within the memory device.

8. The method of claim 7, wherein the recited steps are initiated in the recited order.

9. The method of claim 7, wherein the memory device is a burst extended data out dynamic random access memory device.

10. A method of operating a system including a memory device having a standard DRAM pinout, the method comprising:

inputting a single address to the memory device;

inputting a control signal to the memory device;

sequentially outputting two or more bytes from the memory device based on the single address input and two or more corresponding transitions of the control signal, wherein sequentially outputting two or more bytes from the memory device is based on the single address and the count of the address counter within the memory device; and

changing a count of an address counter within the memory device in response to transitions in the control signal, wherein changing the count of the address counter comprises advancing the count according a linear or interleaved sequence.

11. The method of claim 10, wherein the recited steps are initiated in the recited order.

12. The method of claim 10, wherein the memory device is a burst extended data out dynamic random access memory device.

13. A method of operating a system including a memory device, the method comprising:

inputting a single address to the memory device;

inputting a control signal to the memory device; and

sequentially outputting two or more bytes from the memory device based on the single

address input and two or more corresponding transitions of the control signal; and

wherein the memory device pinout includes an /RAS input pin, an /CAS input pin, an /WE input pin, eight or more address input pins, two or more data output pins, and an /OE input pin.

14. The method of claim 13, wherein the recited steps are initiated in the recited order.

15. The method of claim 13, wherein the memory device is a burst extended data out dynamic random access memory device.

16. A method of operating a system including a memory device having a standard DRAM pinout, the method comprising:

inputting a single address to the memory device, wherein the single address is a column address;

inputting a control signal to the memory device; and

sequentially outputting two or more bytes from the memory device based on the single address input and two or more corresponding transitions of the control signal.

17. The method of claim 16, wherein the recited steps are initiated in the recited order.

18. The method of claim 16, wherein the memory device is a burst extended data out dynamic random access memory device.

19. A method of operating a system including a memory device having a standard DRAM pinout, the method comprising:

inputting a single address to the memory device;

inputting a control signal to the memory device; and

sequentially outputting two or more bytes from the memory device based on the single address input and two or more corresponding transitions of the control signal, wherein sequentially outputting two or more bytes from the memory device, comprises;

operating two or more output drivers in the memory device to drive a byte from the memory device onto data output pins coupled to the output drivers; and

continuing operation of the drivers to drive the byte onto the data output pins without tri-slating the data output pins during predetermined intervals of a strobe signal on at least one of an /RAS input pin and an /CAS input pin in the memory device.

20. The method of claim 19, wherein the recited steps are initiated in the recited order.

21. The method of claim 19, wherein the memory device is a burst extended data out dynamic random access memory device.

22. The method of claim 19, wherein inputting the single address to the memory device comprises:

inputting the single address to a memory device having a pinout consisting of a /RAS input pin, a /CAS input pin, a /WE input pin, eight or more address input pins, two or more data output pins, and a /OE input pin.