Integrated frequency translation and selectivity

• US 7,076,011 B2
• Filed: 02/07/2003
• Issued: 07/11/2006
• Est. Priority Date: 10/21/1998
• Status: Expired due to Term

• Current Assignee: ParkerVision, Inc.
• Original Assignee: ParkerVision, Inc.
• Inventors: Sorrells, David F, Moses, Charley D Jr., Looke, Richard C, Bultman, Michael J, Cook, Robert W
• Primary Examiner(s): PHU, PHUONG M
• Application Number:
  US10/359,636
• Publication Number:
  US 20030112895A1
• Time in Patent Office: 1,250 Days
• Field of Search: 375/350, 375/316, 375/324, 375/328, 375/351, 455/313, 455/296, 455/323, 455/307, 329/304
• US Class Current: 375/350
• CPC Class Codes: H03D 7/00 Transference of modulation from one carrier to another, e.g. frequency-changing H03D9/00, H03D11/00 take precedence; dielectric amplifiers, magnetic amplifiers, parametric amplifiers used as a frequency-changers H03F
• CPC Class Codes: H04B 7/12 Frequency diversity

Abstract

Methods and apparatuses for frequency selectivity and frequency translation, and applications for such methods and apparatuses, are described herein. The method includes steps of filtering an input signal, and down-converting the filtered input signal. The filtering and the down-conversion operations are performed in an integrated, unified manner. The apparatus described herein can be implemented as an integrated circuit (IC).

Claims

1. An apparatus for down-converting and filtering an input signal, comprising:

a frequency down-converter that includes a switch and a capacitor, wherein the switch undersamples the input signal according to a periodic control signal to produce a down-converted signal, wherein a period of said control signal is defined by a first phase and a second phase, wherein said first phase and said second phase each include a respective pulse having a pulse width, wherein said pulse during said first phase of said control signal causes said switch to close and sub-sample the input signal over said pulse of said first phase, wherein energy is transferred from the input signal and stored in said capacitor during said pulse of said first phase, and wherein an instance of the down-converted signal is generated from the transferred energy;

a first delay module that delays said down-converted signal;

a first scaling module that scales an output of said first delay module;

a second delay module that delays said output of said first delay module;

a second scaling module that scales an output of said second delay module; and

an adder that sums at least said output of said first scaling module and said output of said second scaling module, to generate a filtered and down-converted output signal.

2. The apparatus of claim 1, further comprising:

a buffer that buffers said down-converted signal prior to being delayed by said first delay module.

3. The apparatus of claim 1, further comprising:

a third delay module that delays said output of said second delay module; and

a third scaling module that scales an output of said third delay module;

wherein said adder sums said output of said first scaling module, said output of said second scaling module, and said output of said third scaling module, to generate said filtered and down-converted output signal.

4. The apparatus of claim 1, further comprising:

N additional delay modules, wherein N≧

2,

wherein a number 1 additional delay module of said N additional delay modules delays said output of said second delay module, and

wherein a number M additional delay module of said N additional delay modules delays an output of a number M−

1 additional delay module of said N additional delay modules, where N≧

M≧

2; and

N scaling modules that each scale an output of a corresponding one of said N additional delay modules to produce N scaled outputs;

wherein said adder sums said output of said first scaling module, said output of said second scaling module, and said N scaled outputs, to generate said filtered and down-converted output signal.

5. The apparatus of claim 1, wherein said first delay module and said second delay module are analog delay modules.

6. The apparatus of claim 1, wherein said first delay module and said second delay module delay according to said control signal.

7. The apparatus of claim 1, wherein said first delay module comprises:

a second switch that has an input port coupled to said down-converted signal, wherein said second switch is closed during said pulse of said second phase of said control signal;

a first buffer that has an input port coupled to an output port of said second switch;

a second capacitor that has a first terminal coupled to said input port of said first buffer, wherein said second capacitor has a second terminal coupled to a voltage potential.

8. The apparatus of claim 7, wherein said second delay module comprises:

a third switch that has an input port coupled to said output port of said first buffer, wherein said third switch is closed during said pulse of said first phase of said control signal;

a second buffer that has an input port coupled to an output port of said third switch;

a third capacitor that has a first terminal coupled to said input port of said second buffer, wherein said third capacitor has a second terminal coupled to said voltage potential;

a fourth switch that has an input port coupled to an output port of said second buffer wherein said fourth switch is closed during said pulse of said second phase of said control signal;

a third buffer that has an input port coupled to an output port of said fourth switch, and said third buffer has an output port coupled to an input of said second scaling module; and

a fourth capacitor that has a first terminal coupled to said input port of said third buffer, wherein said fourth capacitor has a second terminal coupled to a voltage potential.

9. The apparatus of claim 1, further comprising:

a third delay module that delays said filtered and down-converted output signal; and

a third scaling module that scales an output of said third delay module;

wherein said adder sums at least said output of said first scaling module, said output of said second scaling module, and said output of said third scaling module, to generate said filtered and down-converted output signal.

10. The apparatus of claim 9, further comprising:

a fourth delay module that delays said output of said third delay module; and

a fourth scaling module that scales an output of said fourth delay module;

wherein said adder sums at least said output of said first scaling module, said output of said second scaling module, said output of said third scaling module, and said output of said fourth scaling module, to generate said filtered and down-converted output signal.

11. The apparatus of claim 9, further comprising:

N additional delay modules, wherein N≧

2,

wherein a number 1 additional delay module of said N additional delay modules delays said output of said third delay module, and

wherein a number M additional delay module of said N additional delay modules delays an output of a number M−

1 additional delay module of said N additional delay modules, where N≧

M≧

2; and

N scaling modules that each scale an output of a corresponding one of said N additional delay modules to produce N scaled outputs;

wherein said adder sums said output of said first scaling module, said output of said second scaling module, said output of said third scaling module, and said N scaled outputs, to generate said filtered and down-converted output signal.

12. The apparatus of claim 9, wherein said third delay module is an analog delay module.

13. The apparatus of claim 9, wherein said third delay module delays according to said control signal.

14. The apparatus of claim 9, wherein said third delay module comprises:

a second switch that has an input port coupled to said filtered and down-converted output signal, wherein said second switch is closed during said pulse of said first phase of said control signal;

a first buffer that has an input port coupled to an output port of said second switch;

a second capacitor that has a first terminal coupled to said input port of said first buffer, wherein said second capacitor has a second terminal coupled to a voltage potential;

a third switch that has an input port coupled to an output port of said first buffer wherein said third switch is closed during said pulse of said second phase of said control signal;

a second buffer that has an input port coupled to an output port of said third switch, and said second buffer has an output port coupled to an input of said third scaling module; and

a third capacitor that has a first terminal coupled to said input port of said second buffer, wherein said third capacitor has a second terminal coupled to a voltage potential.

15. An apparatus for down-converting and filtering an input signal, comprising:

a frequency down-converter that includes a switch and a capacitor, wherein the switch undersamples the input signal according to a periodic control signal to produce a down-converted signal, wherein a period of said control signal is defined by a first phase and a second phase, wherein said first phase and said second phase each include a respective pulse having a pulse width, wherein said pulse during said first phase of said control signal causes said switch to close and sub-sample the input signal over said pulse of said first phase, wherein energy is transferred from the input signal and stored in said capacitor during said pulse of said first phase, and wherein an instance of the down-converted signal is generated from the transferred energy;

a first delay module that delays said down-converted signal;

a first scaling module that scales an output of said first delay module;

a second delay module that delays a filtered and down-converted output signal;

a second scaling module that scales an output of said second delay module; and

an adder that sums at least said output of said first scaling module and said output of said second scaling module, to generate said filtered and down-converted output signal.

16. The apparatus of claim 15, further comprising:

a buffer that buffers said down-converted signal prior to being delayed by said first delay module.

17. The apparatus of claim 15, wherein said first delay module and said second delay module are analog delay modules.

18. The apparatus of claim 15, wherein said first delay module and said second delay module delay according to said control signal.

19. The apparatus of claim 15, wherein said first delay module comprises:

a second switch that has an input port coupled to said down-converted signal, wherein said second switch is closed during said pulse of said second phase of said control signal;

a first buffer that has an input port coupled to an output port of said second switch;

a second capacitor that has a first terminal coupled to said input port of said first buffer, wherein said second capacitor has a second terminal coupled to a voltage potential.

20. The apparatus of claim 15, wherein said second delay module comprises:

a second switch that has an input port coupled to said filtered and down-converted output signal, wherein said second switch is closed during said pulse of said first phase of said control signal;

a first buffer that has an input port coupled to an output port of said second switch;

a second capacitor that has a first terminal coupled to said input port of said first buffer, wherein said second capacitor has a second terminal coupled to a voltage potential;

a third switch that has an input port coupled to an output port of said first buffer wherein said third switch is closed during said pulse of said second phase of said control signal;

a second buffer that has an input port coupled to an output port of said third switch, and said second buffer has an output port coupled to an input of said second scaling module; and

a third capacitor that has a first terminal coupled to said input port of said second buffer, wherein said third capacitor has a second terminal coupled to a voltage potential.

21. The apparatus of claim 15, further comprising:

a third delay module that delays said output of said second delay module; and

a third scaling module that scales an output of said third delay module;

wherein said adder sums at least said output of said first scaling module, said output of said second scaling module, and said output of said third scaling module, to generate said filtered and down-converted output signal.

22. The apparatus of claim 15, further comprising:

N additional delay modules, wherein N≧

2,

wherein a number 1 additional delay module of said N additional delay modules delays said output of said second delay module, and

wherein a number M additional delay module of said N additional delay modules delays an output of a number M−

1 additional delay module of said N additional delay modules, where N≧

M≧

2; and

N scaling modules that each scale an output of a corresponding one of said N additional delay modules to produce N scaled outputs;

wherein said adder sums said output of said first scaling module, said output of said second scaling module, and said N scaled outputs, to generate said filtered and down-converted output signal.

23. A method for down-converting and filtering an input signal, comprising:

(1) receiving a periodic control signal having a period defined by a first phase and a second phase, wherein the first phase and the second phase each include a respective pulse having a pulse width;

(2) undersampling the input signal according to the periodic control signal to produce a down-converted signal, comprising

(a) sub-sampling the input signal over the pulse of the first phase to transfer energy from the input signal,

(b) storing the energy transferred during the pulse, and

(c) generating an instance of the down-converted signal from the transferred energy;

(3) delaying the down-converted signal;

(4) scaling the delayed down-converted signal;

(5) delaying the scaled delayed down-converted signal;

(6) scaling the scaled and twice delayed down-converted signal; and

(7) summing the scaled delayed down-converted signal and the twice-scaled twice-delayed down-converted signal to generate a filtered and down-converted output signal.

24. The method of claim 23, further comprising:

(8) buffering the down-converted signal prior to step (3).

25. The method of claim 23, further comprising:

(8) delaying the scaled and twice delayed down-converted signal; and

(9) scaling the scaled and three times delayed down-converted signal;

wherein step (7) comprises summing the scaled delayed down-converted signal, the twice-scaled twice-delayed down-converted signal, and the twice-scaled and three times delayed down-converted signal to generate the filtered and down-converted output signal.

26. The method of claim 23, further comprising:

(8) delaying and scaling the scaled and twice-delayed down-converted signal at least one additional time; and

wherein step (7) comprises summing the scaled delayed down-converted signal, the twice-scaled twice-delayed down-converted signal, and the at least one additional delayed and scaled down-converted signal to generate the filtered and down-converted output signal.

27. The method of claim 23, wherein the input signal, the down-converted signal, and the scaled delayed down-converted signal are analog signals,

wherein step (3) comprises delaying the analog down-converted signal, and

wherein step (5) comprises delaying the analog scaled delayed down-converted signal.

28. The method of claim 23, wherein step (3) comprises delaying the down-converted signal according to the control signal;

and

wherein step (5) comprises delaying the scaled delayed down-converted signal according to the control signal.

29. The method of claim 23, wherein step (3) comprises:

receiving the down-converted signal at an input to a switch;

controlling the switch with the control signal such that the switch is closed during the pulse of the second phase of the control signal;

storing an output of the switch; and

buffering the output of the switch.

30. The method of claim 29, wherein step (5) comprises:

receiving the buffered output of the first switch at an input to a second switch;

controlling the second switch with the control signal such that the second switch is closed during the pulse of the first phase of the control signal;

storing an output of the second switch;

buffering the output of the second switch;

receiving the buffered output of the second switch at an input to a third switch;

controlling the third switch with the control signal such that the third switch is closed during the pulse of the second phase of the control signal;

storing an output of the third switch; and

buffering the output of the third switch.

31. The method of claim 23, further comprising:

(8) delaying the filtered and down-converted output signal; and

(9) scaling the delayed filtered and down-converted output signal;

wherein step (7) comprises summing the scaled delayed down-converted signal, the twice-scaled twice-delayed down-converted signal, and the scaled delayed filtered and down-converted output signal, to generate the filtered and down-converted output signal.

32. The method of claim 31, further comprising:

(10) delaying the delayed filtered and down-converted output signal; and

(11) scaling the twice-delayed filtered and down-converted output signal;

wherein step (7) comprises summing the scaled delayed down-converted signal, the twice-scaled twice-delayed down-converted signal, the scaled delayed filtered and down-converted output signal, and the scaled twice-delayed filtered and down-converted output signal, to generate the filtered and down-converted output signal.

33. The method of claim 31, further comprising:

(10) delaying and scaling the scaled delayed filtered and down-converted output signal at least one additional time; and

wherein step (7) comprises summing the scaled delayed down-converted signal, the twice-scaled twice-delayed down-converted signal, the scaled delayed filtered and down-converted output signal, and the at least one additional delayed and scaled scaled delayed filtered and down-converted output signal, to generate the filtered and down-converted output signal.

34. The method of claim 31, wherein the filtered and down-converted output signal is an analog signal, wherein step (8) comprises delaying the analog filtered and down-converted output signal.

35. The method of claim 31, wherein step (8) comprises delaying the filtered and down-converted output signal according to the control signal.

36. The method of claim 31, wherein step (8) comprises:

receiving the filtered and down-converted signal at an input to a first switch;

controlling the first switch with the control signal such that the first switch is closed during the pulse of the first phase of the control signal;

storing an output of the first switch;

buffering the output of the first switch;

receiving the buffered output of the first switch at an input to a second switch;

controlling the second switch with the control signal such that the second switch is closed during the pulse of the second phase of the control signal;

storing an output of the second switch; and

buffering the output of the second switch.

37. A method for down-converting and filtering an input signal, comprising:

(1) receiving a periodic control signal having a period defined by a first phase and a second phase, wherein the first phase and the second phase each include a respective pulse having a pulse width;

(2) undersampling the input signal according to the periodic control signal to produce a down-converted signal, comprising

(a) sub-sampling the input signal over the pulse of the first phase to transfer energy from the input signal,

(b) storing the energy transferred during the pulse, and

(c) generating an instance of the down-converted signal from the transferred energy;

(3) delaying the down-converted signal;

(4) scaling the delayed down-converted signal;

(5) delaying a filtered and down-converted signal;

(6) scaling the delayed filtered and down-converted signal; and

(7) summing the scaled delayed down-converted signal and scaled delayed filtered and down-converted signal to generate the filtered and down-converted output signal.

38. The method of claim 37, further comprising:

(8) buffering the down-converted signal prior to step (3).

39. The method of claim 37, wherein the input signal, the down-converted signal, and the scaled delayed filtered and down-converted signal are analog signals,

wherein step (3) comprises delaying the analog down-converted signal, and

wherein step (5) comprises delaying the analog filtered and down-converted signal.

40. The method of claim 37, wherein step (3) comprises delaying the down-converted signal according to the control signal;

and

wherein step (5) comprises delaying the filtered and down-converted signal according to the control signal.

41. The method of claim 37, wherein step (3) comprises:

receiving the down-converted signal at an input to a switch;

controlling the switch with the control signal such that the switch is closed during the pulse of the second phase of the control signal;

storing an output of the switch; and

buffering the output of the switch.

42. The method of claim 41, wherein step (5) comprises:

receiving the filtered and down-converted signal at an input to a second switch;

controlling the second switch with the control signal such that the second switch is closed during the pulse of the first phase of the control signal;

storing an output of the second switch;

buffering the output of the second switch;

receiving the buffered output of the second switch at an input to a third switch;

controlling the third switch with the control signal such that the third switch is closed during the pulse of the second phase of the control signal;

storing an output of the third switch; and

buffering the output of the third switch.

43. The method of claim 37, further comprising:

(8) delaying the delayed filtered and down-converted output signal; and

(9) scaling the twice-delayed filtered and down-converted output signal;

wherein step (7) comprises summing the scaled delayed down-converted signal, the scaled delayed filtered and down-converted signal, and the scaled twice-delayed filtered and down-converted output signal, to generate the filtered and down-converted output signal.

44. The method of claim 37, further comprising:

(8) delaying and scaling the delayed filtered and down-converted signal at least one additional time; and

wherein step (7) comprises summing the scaled delayed down-converted signal, the scaled delayed filtered and down-converted signal, and the at least one additional delayed and scaled filtered and down-converted signal to generate the filtered and down-converted output signal.