Variable gain amplifier for low voltage applications

• US 7,076,226 B2
• Filed: 12/30/2003
• Issued: 07/11/2006
• Est. Priority Date: 12/20/1999
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Vorenkamp, Pieter, Bult, Klaas, Venes, Arnoldus, van de Plassche, Rudy
• Primary Examiner(s): Vuong, Quochien B.
• Application Number:
  US10/747,124
• Publication Number:
  US 20040219898A1
• Time in Patent Office: 924 Days
• Field of Search: 455/127.2, 455/232.1, 455/234.1, 455/245.1, 455/250.1, 455/252.1, 330/69, 330/250, 330/252, 330/254, 330/278
• US Class Current: 455/252.1
• CPC Class Codes: H03F 1/34 Negative-feedback-circuit arrangements with or without positive feedback H03F1/02 - H03F1/30, H03F1/38 - H03F1/50, H03F3/50 take precedence ; for rejection of common mode signals H03F3/45479
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 2200/513 the amplifier being made for low supply voltages
• CPC Class Codes: H03F 2203/45644 the LC comprising a cross coupling circuit, e.g. comprising two cross-coupled transistors
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H03F 3/45188 Non-folded cascode stages
• CPC Class Codes: H03F 3/45192 Folded cascode stages
• CPC Class Codes: H03G 1/0029 using FETs
• CPC Class Codes: H03G 3/30 in amplifiers having semiconductor devices
• CPC Class Codes: H04B 2001/0433 with linearisation using feedback

Abstract

An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.

Claims

1. A method for controlling transconductance gain of a complementary differential amplifier having first and second differential pairs of transistors, comprising:

applying a first input voltage to a first transistor gate of the first differential pair of transistors;

applying a second input voltage to a second transistor gate of the second differential pair of transistors; and

varying a current source for at least one of the first and second differential pairs of transistors to control transconductance gain of the complementary differential amplifier for varying input voltages.

2. The method as recited in claim 1, further comprising varying the current source for at least one of the differential pairs of transistors to provide a linear transconductance gain of the complementary differential amplifier.

3. The method as recited in claim 1, further comprising varying the current source for at least one of the differential pairs of transistors as a function of at least one of the first input voltage, the second input voltage, and the difference between the first and second input voltages.

4. A method for controlling transconductance gain of a complementary differential amplifier over a range of input voltages, the complementary differential pair amplifier having first and second differential pairs of transistors, comprising:

applying a first input voltage to a first transistor gate of the first differential pair of transistors;

applying a second input voltage to a second transistor gate of the second differential pair of transistors;

varying a current source for at least one pair of the differential pairs of transistors to control transconductance gain of the complementary differential amplifier for varying input voltages; and

applying a differential reference voltage across a resistive ladder connected between respective second transistor gates of the first differential pair of transistors and respective first transistor gates of the second differential pair of transistors.

5. The method as recited in claim 4, further comprising varying the differential reference voltage to control the range of input voltages.

6. The method as recited in claim 4, further comprising varying the differential reference voltage to expand the range of input voltages.

7. The method as recited in claim 4, further comprising varying the current source for at least one of the differential pairs of transistors to provide a linear transconductance gain of the complementary differential amplifier.

8. The method as recited in claim 4, further comprising varying the current source for at least one of the differential pairs of transistors as a function of at least one of the first input voltage, the second input voltage, and the difference between the first and second input voltages.