Emulator chip/board architecture and interface

• US 7,076,420 B1
• Filed: 10/10/2001
• Issued: 07/11/2006
• Est. Priority Date: 10/26/2000
• Status: Expired due to Fees

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Snyder, Warren, Nemecek, Craig, Sullam, Bert
• Primary Examiner(s): Rodriguez, Paul L.
• Assistant Examiner(s): Craig, Dwin M.
• Application Number:
  US09/975,030
• Time in Patent Office: 1,735 Days
• Field of Search: 703/28, 714/28
• US Class Current: 703/28
• CPC Class Codes: G06F 11/3656 using a specific debug interface

Abstract

A communication interface for an in-circuit emulation system. The interface uses four pins between a virtual microcontroller (an FPGA emulating a microcontroller) and a real microcontroller under test. The bus is fast enough to allow the two devices to operate in synchronization. I/O reads, interrupt vector information and watchdog information is provided over the bus in a time fast enough to allow execution in lock step. Two data lines are provided, one is bi-directional and one is driven only by the microcontroller. A system clock is provided and the microcontroller supplies its clock signal to the FPGA since the microcontroller can operate at varying clock speeds. The bus is time-dependent so more information can be placed on this reduced-pin count bus. Therefore, instructions and data are distinguished based on the time the information is sent within the sequence. The bus can be used to carry trace information, program the flash memory on the microcontroller, perform test control functions, etc.

Claims

1. A communication interface for coupling a device (DUT) under test with an emulator device, the emulator device implementing the DUT and executing instruction in lock-step with the DUT, the communication interface comprising:

a time dependent data transport portion that communicates serialized data between the DUT and the emulator device; and

a clock portion that supplies clock information to the DUT and the emulator device;

wherein

the time dependent data transport portion transports varying types of information depending upon a time phase of operation of the DUT and the emulator device.

2. The communication interface according to claim 1, wherein the time dependent data transport portion comprises a plurality of data lines, at least one of which caries bi-directional data.

3. The communication interface according to claim 1, wherein the time dependent data transport portion comprises:

a first time dependent unidirectional data line that carries data from the DUT to the emulator devices; and

a second bi-directional time dependent data line.

4. The communication interface according to claim 1, wherein the DUT can operate at varying clock speeds and wherein the clock portion comprises:

a system clock line; and

a line for supplying an internal clock signal from the DUT to the emulator device.

5. A communication interface, comprising:

an interface;

a microcontroller;

an emulator device implementing a microcontroller and executing instructions;

wherein the microcontroller is coupled to the emulator device via the interface, the microcontroller executing the instructions in lock-step with the emulator device; and

wherein the interface comprises;

a first time dependent data line;

a second bi-directional time dependent data line;

a third line for supplying an internal clock signal from the microcontroller; and

a system clock line.

6. The communication interface according to claim 5, wherein the emulator device comprises a field programmable gate array (FPGA).

7. The communication interface according to claim 5, wherein the first time dependent data line is used to convey information regarding pending interrupts.

8. The communication interface according to claim 5, wherein the second bi-direction time dependent data line carries break signals.

9. The communication interface according to claim 5, wherein the interface lines are carried over a Category five cable.

10. The communication interface according to claim 5, wherein register read/write commands are conveyed over the first and second data lines when the microcontroller is in a halted mode.

11. The communication interface according to claim 5, wherein the first and second data lines are used to convey register information from the microcontroller to the emulator device when the microcontroller is in a halted mode.

12. The communication interface according to claim 5, wherein the first and second data lines are used to communicate I/O read, interrupt vector and watchdog timer information when the microcontroller is running.

13. The communication interface according to claim 5, wherein commands and data for the microcontroller are communicated over the interface for programming flash memory forming a part of the microcontroller.

14. The communication interface according to claim 5, wherein the clock frequency of the microcontroller is programmable, and wherein the clock is supplied to the emulator devices over the third line of the interface.

15. The communication interface according to claim 5, wherein the microcontroller transfers I/O data over the interface at a rate adequate to permit the emulator device to process the I/O data before execution of a next instruction and thus keep the microcontroller and the emulation device in synchronization.

16. The communication interface according to claim 5, wherein the microcontroller uses the interface to return register information when in a halted mode, and to send I/O read, interrupt vector, and watchdog information when not in a halted mode.

17. A four-wire interface for use in an in-circuit emulation (ICE) system to couple a microcontroller with an emulator device functioning as a virtual microcontroller, comprising:

a first interface line carrying a system clock driven by the microcontroller, for driving the communication state machines forming a part of the virtual microcontroller;

a second interface line carrying an internal microcontroller CPU clock;

a third interface line for use by the microcontroller to send I/O data to the ICE and to notify the ICE of pending interrupts; and

a fourth interface line for bi-directional communication that is used by the microcontroller to send I/O data to the ICE, and that is used by the ICE to convey halt requests to the microcontroller.

18. The apparatus according to claim 17, wherein the system clock runs at a first clock rate, unless the internal microcontroller CPU clock is running at the first clock rate in which case the system clock switches to two times the first clock rate.

19. The apparatus according to claim 17, wherein the interface lines are carried over a Category five cable.

20. The apparatus according to claim 17, wherein register read/write commands are conveyed over the third and fourth interface lines when the microcontroller is in a halted mode.

21. The apparatus according to claim 17, wherein the third and fourth interface lines are used to convey register information from the microcontroller to the emulator device when the microcontroller is in a halted mode.

22. The apparatus according to claim 17, wherein the third and fourth interface lines are used to communicate I/O read, interrupt vector and watchdog timer information when the microcontroller is running.

23. The apparatus according to claim 17, wherein commands and data for the microcontroller are communicated over the third and fourth interface lines for programming flash memory forming a part of the microcontroller.

24. The apparatus according to claim 17, wherein test and control functions are carried over the third and fourth interface lines to carry out real-time trace functions.

25. The apparatus according to claim 17, wherein the microcontroller sends I/O data over the interface at a rate adequate to keep the microcontroller and the emulation device in synchronization.

26. A four wire interface for use in an in-circuit emulation (ICE) system to couple a microcontroller with an emulator device based on a field programmable gate array (FPGA) functioning as a virtual microcontroller, comprising:

a first interface line carrying a system clock driven by the microcontroller, for driving the communication state machines forming a part of the virtual microcontroller;

a second interface line carrying an internal microcontroller CPU clock, where in the clock frequency of the microcontroller is programmable;

wherein the system clock runs at a first clock rate, unless the internal microcontroller CPU clock is running at the first clock rate in which case the system clock switches to two times the first clock rate;

a third interface line for use by the microcontroller to send I/O data to the ICE and to notify the ICE of pending interrupts;

a fourth interface line used for bi-directional communication that is used by the microcontroller to send I/O data to the ICE, and that is used by the ICE to convey halt requests to the microcontroller;

wherein register read/write commands are conveyed over the third and fourth interface lines when the microcontroller is in a halted mode and wherein the third and fourth interface lines are used to communicated I/O read, interrupt vector and watchdog timer information when the microcontroller is running;

wherein test and control functions are carried over the third and fourth interface lines to carry out real-time trace functions;

wherein the microcontroller sends I/O data over the interface at a rate adequate to keep the microcontroller and the emulation device in synchronization; and

wherein the interface lines are carried over a Category five cable.