Cache line pre-load and pre-own based on cache coherence speculation
First Claim
1. A processor comprising:
- a bus interface to provide communication with other processors;
a local cache;
a cache invalidation history table associated with the local cache; and
a cache controller associated with the local cache, the cache controller to track invalidated cache lines by recording the line addresses of invalidated cache lines and an indicator indicating whether each of the invalidated cache lines recorded was invalidated via a clean-invalidate or a dirty-invalidate in the invalidation history table, the cache controller further to revalidate only those invalidated cache lines recorded in the invalidation history table as having been clean-invalidate invalidated, wherein the revalidate includes monitoring the bus for cache line addresses of clean-invalidate invalidated cache lines recorded in the invalidation history table and for associated cache line data, and includes updating the invalidated cache line data with the cache line data associated with the recorded cache line addresses.
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Abstract
The invention provides a cache management system comprising in various embodiments pre-load and pre-own functionality to enhance cache efficiency in shared memory distributed cache multiprocessor computer systems. Some embodiments of the invention comprise an invalidation history table to record the line addresses of cache lines invalidated through dirty or clean invalidation, and which is used such that invalidated cache lines recorded in an invalidation history table are reloaded into cache by monitoring the bus for cache line addresses of cache lines recorded in the invalidation history table. In some further embodiments, a write-back bit associated with each L2 cache entry records when either a hit to the same line in another processor is detected or when the same line is invalidated in another processor'"'"'s cache, and the system broadcasts write-backs from the selected local cache only when the line being written back has a write-back bit that has been set.
50 Citations
17 Claims
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1. A processor comprising:
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a bus interface to provide communication with other processors; a local cache; a cache invalidation history table associated with the local cache; and a cache controller associated with the local cache, the cache controller to track invalidated cache lines by recording the line addresses of invalidated cache lines and an indicator indicating whether each of the invalidated cache lines recorded was invalidated via a clean-invalidate or a dirty-invalidate in the invalidation history table, the cache controller further to revalidate only those invalidated cache lines recorded in the invalidation history table as having been clean-invalidate invalidated, wherein the revalidate includes monitoring the bus for cache line addresses of clean-invalidate invalidated cache lines recorded in the invalidation history table and for associated cache line data, and includes updating the invalidated cache line data with the cache line data associated with the recorded cache line addresses. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A cache control module, comprising:
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an interface to a local cache; and a cache controller to track invalidated cache lines by recording the line addresses of invalidated cache lines and an indicator indicating whether each of the invalidated cache lines recorded was invalidated via a clean-invalidate or a dirty-invalidate in an invalidation history table, the cache controller further to revalidate only those invalidated cache lines recorded in the invalidation history table as having been clean-invalidate invalidated, wherein the revalidate includes monitoring the bus for cache line addresses of clean-invalidate invalidated cache lines recorded in the invalidation history table and for associated cache line data, and includes updating the invalidated cache line data with the cache line data associated with the recorded cache line addresses. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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Specification