Processor that eliminates mis-steering instruction fetch resulting from incorrect resolution of mis-speculated branch instructions
First Claim
1. A pipelined processor comprising:
- an instruction fetcher capable of fetching instructions from an instruction source;
a branch resolver coupled to the instruction fetcher and capable of resolving a branch instruction;
a delay element coupled between the branch resolver and the instruction fetcher, the delay element to allow for determination of whether the branch instruction has been resolved correctly;
replay logic coupled to the instruction fetcher and capable of determining a replay condition; and
logic coupled to receive input from the replay logic and input from the branch resolver, and the logic coupled to supply output to the instruction fetcher for determining a fetch operation of the instruction fetcher, wherein the logic selects either input from the branch resolver or input from the replay logic, wherein the output supplied to the instruction fetcher is the input selected by the logic, and wherein the input from the branch resolver is delayed by the delay element.
2 Assignments
0 Petitions
Accused Products
Abstract
A processor avoids or eliminates repetitive replay conditions and frequent instruction resteering through various techniques including resteering the fetch after the branch instruction retires, and delaying branch resolution. A processor resolves conditional branches and avoids repetitive resteering by delaying branch resolution. The processor has an instruction pipeline with inserted delay in branch condition and replay control pathways. For example, an instruction sequence that includes a load instruction followed by a subtract instruction then a conditional branch, delays branch resolution to allow time for analysis to determine whether the condition branch has resolved correctly. Eliminating incorrect branch resolutions prevents flushing of correctly predicted branches.
40 Citations
15 Claims
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1. A pipelined processor comprising:
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an instruction fetcher capable of fetching instructions from an instruction source; a branch resolver coupled to the instruction fetcher and capable of resolving a branch instruction; a delay element coupled between the branch resolver and the instruction fetcher, the delay element to allow for determination of whether the branch instruction has been resolved correctly; replay logic coupled to the instruction fetcher and capable of determining a replay condition; and logic coupled to receive input from the replay logic and input from the branch resolver, and the logic coupled to supply output to the instruction fetcher for determining a fetch operation of the instruction fetcher, wherein the logic selects either input from the branch resolver or input from the replay logic, wherein the output supplied to the instruction fetcher is the input selected by the logic, and wherein the input from the branch resolver is delayed by the delay element. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A pipelined processor comprising:
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an instruction fetcher capable of fetching instructions from an instruction source; a branch resolver coupled to the instruction fetcher and capable of resolving a branch instruction; a delay element coupled between the branch resolver and the instruction fetcher, the delay element to allow for determination of whether the branch instruction has been resolved correctly; a load miss buffer operable to indicate detection of a replay condition for load instructions; and the instruction fetcher coupled with the load miss buffer, the instruction fetcher operable to fetch instructions based at least in part on both replay condition indications from the load miss buffer and branch instruction resolution indications from the branch resolver. - View Dependent Claims (11, 12, 13, 14, 15)
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Specification