Method and apparatus for communicating securely with a token

• US 7,076,669 B2
• Filed: 04/15/2002
• Issued: 07/11/2006
• Est. Priority Date: 04/15/2002
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Poisner, David I., Grawrock, David W., Sutton, James A.
• Primary Examiner(s): Peeso, Thomas R.
• Application Number:
  US10/122,544
• Publication Number:
  US 20030196088A1
• Time in Patent Office: 1,548 Days
• Field of Search: 713/200, 713/201
• US Class Current: 726/22
• CPC Class Codes: G06F 21/78 to assure secure storage of data address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00
• CPC Class Codes: G06F 21/85 interconnection devices, e.g. bus-connected or in-line devices

Abstract

A method and apparatus to communicate with a token using a previously reserved binary number in the start field of a cycle, wherein the cycle is not echoed on any bus other than the bus through which the communication is received.

Claims

1. An apparatus comprising:

a processor coupled to a first bus to issue a trusted request;

a token; and

a chipset coupled to the processor by the first bus, said chipset coupled to the token by a second bus, said chipset to decode the trusted request from the processor and to forward the trusted request to the token, said chipset to prevent the trusted request from being echoed on one or more busses other than the second bus.

2. The apparatus of claim 1 wherein the first bus is a front side bus (FSB) and the second bus is a low pin count (LPC) bus.

3. The apparatus of claim 2 wherein the chipset sends false data to the one or more busses other than the second bus.

4. The apparatus of claim 1 wherein the trusted request comprises a request that addresses a trusted configuration space.

5. The apparatus of claim 1 wherein the trusted request is issued in response to the processor executing microcode or trusted code.

6. The apparatus of claim 1 wherein the chipset comprises decoder logic to decode an address in the trusted request.

7. The apparatus of claim 1 further comprising the chipset to encode the trusted request to the token to prevent one or more other devices on the second bus from reading the trusted request.

8. A method comprising:

sending by a processor a trusted request to a chipset;

decoding by the chipset the trusted request received from the processor and

forwarding the trusted request via a bus to a token using a code, said code selected such that other devices on the bus ignore the trusted request.

9. The method of claim 8 further comprising suppressing the request on one or more other busses.

10. The method of claim 8 wherein forwarding the request to the token comprises using reserved bits in the request.

11. A chipset comprising:

a first interface logic to receive from a processor a trusted request via a first bus;

a second interface logic coupled to a token via a second bus;

a decoding logic coupled to the first interface logic and the second interface logic, said first interface logic to decode the trusted request, said first interface logic to determine that the trusted request is a trusted request from the processor, said first interface logic to further determine that the trusted request targets the token; and

the first interface logic to forward the trusted request to the second interface logic if the trusted request targets the token, said second interface logic to prevent the trusted request from appearing on any bus other than the first bus and the second bus.

12. The chipset of claim 11 wherein the second interface logic sends false data to any bus other than the first bus and the second bus.

13. The chipset of claim 11 further comprising the second interface logic to encode the trusted request to the token to prevent one or more other devices on the second bus from reading the trusted request.

14. A token comprising:

one or more registers;

an input/output (I/O) bus interface logic to couple the token to a chipset via a bus, said token to receive a trusted request from the chipset, said trusted request to comprise reserved bits that are ignored by one or more devices on the bus.

15. The apparatus of claim 14 wherein the token comprises a bus master engine.

16. The apparatus of claim 14 wherein the trusted request comprises reserved bits comprising any one of 0001, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, and 1110.

17. An apparatus comprising:

a chipset to generate a low pin count (LPC) cycle to a token on a LPC bus, said LPC cycle comprising a start field comprising any one of 0001, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, and 1110.

18. The apparatus of claim 17 wherein the LPC cycle comprises a start field that comprises at least one binary number in the range 0100 to 1110.

19. The apparatus of claim 17 wherein the chipset is to prevent the LPC cycle from appearing on one or more busses other than the LPC bus.

20. The apparatus of claim 17 wherein the token on the LPC bus is a trusted plafform module (TPM).

21. The apparatus of claim 17 wherein the chipset is to cause information contained in the LPC cycle to be invalid if the LPC cycle is present on one or more busses other than the LPC bus.

22. A machine readable medium comprising instructions which in response to being executed results in a computing device to issue a trusted request from a processor to a chipset, and to forward the trusted request via a bus to a token, said trusted request encoded to form an encoded request such that other devices on the bus ignore the encoded request.

23. The machine readable medium of claim 22 wherein said instructions to forward the request via a bus to a token, said request encoded such that other devices on the bus ignore the encoded request includes further instructions to generate a low pin count (LPC) cycle to the token, said LPC cycle comprising a start field comprising anyone of 0001, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, and 1110.

24. The machine readable medium of claim 22 wherein the trusted request comprises instructions to address a trusted configuration space in the chipset.

25. The machine readable medium of claim 22 wherein the chipset is to prevent the encoded request from appearing on one or more busses other than the bus.

26. A chipset comprising:

a dual ported register, said dual ported register to couple a processor to a token, said dual ported register to receive a value for the token from the processor, said processor to write to the token to inform the token to obtain the value from the dual ported register.

27. The chipset of claim 26 further comprising the processor to write to the dual ported register using trusted microcode.

28. The chipset of claim 26 further comprising the processor to write to the token using an input/output write cycle.

29. A method comprising:

writing, using a trusted cycle, data to a dual ported register; and

generating a standard Input/Output (I/O) write cycle to a token to inform the token to read the data from the dual ported register.

30. The method of claim 29 further comprising the token to become a bus master to read the data from the dual ported register.

31. A method comprising:

generating a standard Input/Output (I/O) write cycle to a token to inform the token to write data to a dual ported register; and

reading, using a trusted cycle, from the dual ported register the data written by the token.

32. The method of claim 31 further comprising the token to become a bus master to write data to the dual ported register.