Methodology of locating faults of scan chains in logic integrated circuits

• US 7,076,707 B2
• Filed: 03/31/2003
• Issued: 07/11/2006
• Est. Priority Date: 03/07/2003
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Jen, Chin-pin, Chen, Hung-chieh, Yang, Ming-chang, Lee, Juinn
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Abraham, Esaw
• Application Number:
  US10/401,701
• Publication Number:
  US 20040181722A1
• Time in Patent Office: 1,198 Days
• Field of Search: 714/726, 714/25, 714/30
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318566 Comparators; Diagnosing the device under test
• CPC Class Codes: G01R 31/318569 Error indication, logging circuits
• CPC Class Codes: G01R 31/3191 Calibration

Abstract

For a plurality of logic integrated circuits, initial value vectors associated with flip-flops are retrieved from each of corresponding scan chain sets. The initial value vectors of the same corresponding scan chain set are compared with each other so as to identify elements with fixed values in the initial value vectors. When the total number of the elements with fixed values reaches a predetermined percentage, the elements having fixed values are selected as a golden pattern of the corresponding scan chain set. During the testing, an initial value vector of a scan chain of a logic integrated circuit to be tested is compared with the golden pattern associated with the scan chain, so as to determine whether a faulty flip-flop exists in the scan chain of the logic integrated circuit to be tested.

Claims

1. A method of locating at least one a fault of a scan chain having a plurality of flip-flops in a logic integrated circuit of a configuration, comprising:

an initial value collecting step of randomly selecting a plurality of logic integrated circuits with the same configuration, retrieving a plurality of initial value vectors of the flip-flops of every scan chain within said logic integrated circuits, and grouping together said initial value vectors into a plurality of corresponding scan chain sets, wherein said scan chain set contains scan chains with the same configuration;

a golden pattern determining step of comparing each of the initial value vectors in the same corresponding scan chain set with each other to identify elements of the initial value vectors with fixed values and selecting the elements with the fixed values as a golden pattern for the corresponding scan chain set when the number of said elements reaches a predetermined percentage; and

a fault locating step of comparing a plurality of initial values of a scan chain in question of a logic integrated circuit with the golden pattern found for the corresponding scan chain set that contains scan chains of the same configuration as the scan chain in question to determine whether the scan chain in question has at least one faulty flip-flop.

2. The method according to claim 1, wherein the initial value vector is constructed by a sequence of data stored in the plurality of flip-flops, each of the data being logic 0 or logic 1.

3. The method according to claim 1, wherein the initial value collecting step is performed by using an automatic test equipment.

4. The method according to claim 1, wherein the initial values of the scan chain in question are collect by using an automatic test equipment.

5. The method according to claim 1, wherein the fault locating step further comprises:

locating the at least one faulty flip-flop when the scan chain in question is determined to have the at one faulty flip-flop.

6. The method according to claim 1, wherein the fault locating step further comprises:

finding out at least one faulty position with reference to a layout of the logic integrated circuit containing the scan chain in question when the scan chain in question is determined to have the at least one faulty flip-flop.

7. The method according to claim 1, wherein the at least one faulty flip-flop is caused by a fault located in a range covering all metal wirings associated with the at least one faulty flip-flop.