Identification and implementation of clock gating in the design of integrated circuits
First Claim
Patent Images
1. An integrated circuit (IC) design method, intended for reducing IC power consumption by the efficient identification and implementation of register clock gating in an IC design, comprising:
- identifying candidate registers to be clock gated; and
for each of the candidate registers;
determining an output function of the candidate register;
determining at least one gating condition for the candidate register;
determining at least one hold expression for the candidate register;
performing a feedback loop identification step for the candidate register, including identifying a feedback loop that is free of combinational logic elements, except for combinational logic elements having a function that becomes equivalent to a buffer as a result of setting a control value; and
based on the result of the determining of the output function, the gating condition, and the hold expression, and the identification of the feedback loop, clock gating the candidate register.
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Abstract
Identification and implementation of clock gating in the design of an integrated circuit (IC) is performed with automated assistance. Electrical power consumption is reduced by clock gating. The automated assistance identifies registers that are candidates for clock gating, and highlights, in the IC design, registers associated with a gated clock domain and the logic blocks driven by these registers.
61 Citations
46 Claims
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1. An integrated circuit (IC) design method, intended for reducing IC power consumption by the efficient identification and implementation of register clock gating in an IC design, comprising:
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identifying candidate registers to be clock gated; and for each of the candidate registers; determining an output function of the candidate register; determining at least one gating condition for the candidate register; determining at least one hold expression for the candidate register; performing a feedback loop identification step for the candidate register, including identifying a feedback loop that is free of combinational logic elements, except for combinational logic elements having a function that becomes equivalent to a buffer as a result of setting a control value; and based on the result of the determining of the output function, the gating condition, and the hold expression, and the identification of the feedback loop, clock gating the candidate register. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A computer program product for enabling a computer system to perform operations for an integrated circuit (IC) design method, intended for reducing IC power consumption by the efficient identification and implementation of register clock gating in an IC design, the computer program product having computer instructions on a computer readable medium, the operations comprising:
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identifying candidate registers to be clock gated; and for each of the candidate registers; determining an output function of the candidate register; determining at least one gating condition for the candidate register; determining at least one hold expression for the candidate register; performing a feedback loop identification step for the candidate register, including identifying a feedback loop that is free of combinational logic elements, except for combinational logic elements having a function that becomes equivalent to a buffer as a result of setting a control value; and based on the result of the determining of the output function, the gating condition, and the hold expression, clock gating the candidate register. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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35. A computer system for performing an integrated circuit (IC) design method, intended for reducing IC power consumption by the efficient identification and implementation of register clock gating in an IC design, the computer system having a processor and a memory under control of the processor, the memory including software instructions for performing operations comprising:
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identifying candidate registers to be clock gated; and for each of the candidate registers; determining an output function of the candidate register; determining at least one gating condition for the candidate register; determining at least one hold expression for the candidate register; and performing a feedback loop identification step for the candidate register, including identifying a feedback loop that is free of combinational logic elements, except for combinational logic elements having a function that becomes equivalent to a buffer as a result of setting a control value; and based on the result of the determining of the output function, the gating condition, and the hold expression, and the identification of the feedback loop, clock gating the candidate register. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42, 43)
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44. An integrated circuit visualization tool adapted to implement a method for highlighting gated clock domains and gated registers in a design of an integrated circuit (IC), the visualization tool comprising:
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means for displaying the design of the IC; processing means controlling the means for displaying; and
,a memory, under control of the processing means, including software instructions adapted to enable the processing means to perform the steps of; identifying the clock gated domains in the IC'"'"'s design; for each the gated clock domain, highlighting registers that are connected to the gated clock; tracing forward from each of the highlighted register to detect logic units affected by clock gating of the highlighted register; and highlighting the affected logic units; wherein the memory further comprises software instructions adapted to enable the processing means to identify candidate registers to be clock gated, and, for each of the candidate registers;
determining an output function of the candidate register;
determining at least one gating condition for the candidate register;
determining at least one hold expression for the candidate register;
performing a feedback loop identification step for the candidate register, including identifying a feedback loop that is free of combinational logic elements, except for combinational logic elements having a function that becomes equivalent to a buffer as a result of setting a control value; and
based on the result of the determining of the output function, the gating condition, and the hold expression, and the identification of the feedback loop, clock gating the candidate register. - View Dependent Claims (45, 46)
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Specification