Self-aligned trench MOSFETs and methods for making the same

• US 7,078,296 B2
• Filed: 01/16/2002
• Issued: 07/18/2006
• Est. Priority Date: 01/16/2002
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Murphy, James, Probst, Dean, Herrick, Robert, Losee, Becky, Marchant, Bruce, Chau, Duc
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): GARCIA, JOANNIE A
• Application Number:
  US10/052,234
• Publication Number:
  US 20030132480A1
• Time in Patent Office: 1,644 Days
• Field of Search: 438/242, 438/361, 438/589, 438/667, 438/672, 438/675, 438/695, 438/700, 438/760, 438/259, 438/270, 438/FOR.118, 438/FOR.189, 438/FOR.388, 438/702, 438/703, 438/791
• US Class Current: 438/270
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate

Abstract

Self-aligned trench MOSFETs and methods for manufacturing the same are disclosed. By having a self-aligned structure, the number of MOSFETS per unit area—the cell density—is increased, making the MOSFETs cheaper to produce. The self-aligned structure for the MOSFET is provided by making the sidewall of the overlying isolation dielectric layer substantially aligned with the sidewall of the gate conductor. Such an alignment can be made through any number of methods such as using a dual dielectric process, using a selective dielectric oxidation process, using a selective dielectric deposition process, or a spin-on-glass dielectric process.

Claims

1. A method for making a semiconductor device, comprising:

providing a substrate with an upper surface, the substrate having a trench therein;

providing an oxide layer on a bottom and sidewall of the trench;

providing a conductive layer on a bottom and sidewall of the oxide layer, the conductive layer having an upper surface below the upper surface of the substrate; and

providing a self-aligned isolation cap on the conductive layer within the trench, the isolation cap comprising a non-organic dielectric material, including providing the self-aligned isolation cap by providing a first dielectric layer, providing a second dielectric layer over the first dielectric layer, reflowing the second dielectric layer, and then anisotropically etching the first and second dielectric layers until the upper substrate surface is exposed.

2. The method of claim 1, including reflowing the second dielectric layer until an upper surface of the second dielectric layer is substantially planar.

3. The method of claim 1, wherein the conductive layer comprises polysilicon or metal.

4. The method of claim 1, wherein the self-aligned isolation cap comprises silicon oxide.

5. The method of claim 1, wherein the first dielectric material comprises PSG and the second dielectric material comprises BPSG.

6. A method for making a semiconductor device, comprising:

providing a semiconductor substrate with an upper surface, the substrate having a trench therein;

providing a gate oxide layer on a bottom and sidewall of the trench;

providing a conductive layer on a bottom and sidewall of the oxide layer, the conductive layer having an upper surface below the upper surface of the substrate; and

providing a self-aligned isolation cap on the conductive layer and only within the trench by using a combination of dielectric materials with different etching rates.

7. The method of claim 6, wherein the dielectric materials comprises PSG, BPSG, or a low-temperature oxide.

8. The method of claim 6, wherein the different etching rates are provided by doping one or both of the dielectric materials.

9. The method of claim 7, wherein one of the dielectric materials comprises PSG and another dielectric material comprises BPSG.

10. The method of claim 6, wherein the conductive layer comprises polysilicon or metal.

11. A method for making a semiconductor device, comprising:

providing a substrate with an upper surface, the substrate having a trench therein;

providing an oxide layer on a bottom and sidewall of the trench;

providing a conductive layer on a bottom and sidewall of the oxide layer, the conductive layer having an upper surface below the upper surface of the substrate; and

providing a self-aligned isolation cap on the conductive layer within the trench by using a combination of dielectric materials with different etching rates, including providing the self-aligned isolation cap by providing a first dielectric layer having a first etching rate in the trench and on the upper substrate surface, providing a second dielectric layer having an etching rate faster than the first etching rate on the first dielectric layer, reflowing the first and second dielectric layers, and then isotropically etching until the upper substrate surface is exposed.

12. The method of claim 11, including reflowing the first and second dielectric layers until the upper surface of the second dielectric layer is substantially planar.

13. The method of claim 11, wherein the first dielectric layer dielectric material comprises PSG, BPSG, or a low-temperature oxide.

14. The method of claim 11, wherein the second dielectric layer dielectric material comprises PSG or BPSG.

15. The method of claim 11, wherein the conductive layer comprises polysilicon or metal.

16. A method for making a semiconductor device, comprising:

providing a semiconductor substrate with an upper surface;

providing a nitride-containing layer on a first portion of the substrate upper surface;

providing a trench in a second portion of the substrate, the second portion not containing the nitride-containing layer thereon;

providing a gate oxide layer on a bottom and sidewall of the trench;

providing a conductive layer on a bottom and sidewall of the oxide layer, the conductive layer having an upper surface below the upper surface of the substrate;

providing a self-aligned isolation cap on the conductive layer within the trench; and

removing the nitride-containing layer.

17. The method of claim 16, wherein the upper surface of the conductive layer and the substrate upper surface are separated by about 0.5 microns.

18. The method of claim 16, the conductive layer comprising polysilicon.

19. The method of claim 18, including providing the self-aligned isolation cap by oxidizing the upper surface of the conductive polysilicon layer.

20. The method of claim 16, including providing the self-aligned isolation cap by selectively depositing a dielectric layer on the upper surface of the conductive layer.

21. The method of claim 16, wherein the conductive layer comprises polysilicon or metal.

22. A method for making a MOSFET, comprising:

providing a semiconductor substrate with an upper surface, the substrate having a trench therein;

providing source and channel regions proximate the trench;

providing a gate oxide on a bottom and sidewall of the trench;

providing a conductive gate on a bottom and sidewall of the gate oxide, the conductive gate having an upper surface below the upper surface of the substrate; and

providing a self-aligned isolation cap on the conductive gate within the trench by using a combination of dielectric materials with different etching rates.

23. A method for making a MOSFET, comprising:

providing a substrate with an upper surface, the substrate having a trench therein;

providing source and channel regions proximate the trench;

providing a gate oxide on a bottom and sidewall of the trench;

providing a conductive gate on a bottom and sidewall of the gate oxide, the conductive gate having an upper surface below the upper surface of the substrate; and

providing a self-aligned isolation cap on the conductive gate within the trench by using a combination of dielectric materials with different etching rates, including providing the self-aligned isolation cap by providing a first dielectric layer having a first etching rate in the trench and on the upper substrate surface, providing a second dielectric layer having an etching rate faster than the first etching rate on the first dielectric layer, reflowing the first and second dielectric layers, and then isotropically etching until the upper substrate surface is exposed.

24. A method for making a MOSFET, comprising:

providing a semiconductor substrate with an upper surface;

providing source and channel regions in the substrate;

providing a nitride-containing layer on a first portion of the substrate upper surface;

providing a trench in a second portion of the substrate, the second portion not containing the nitride-containing layer thereon;

providing a gate oxide on a bottom and sidewall of the trench;

providing a conductive gate on a bottom and sidewall of the gate oxide, the conductive gate having an upper surface below the upper surface of the substrate;

providing a self-aligned isolation cap on the conductive gate within the trench; and

removing the nitride-containing layer.