Nonvolatile memory solution using single-poly pFlash technology

• US 7,078,761 B2
• Filed: 03/05/2004
• Issued: 07/18/2006
• Est. Priority Date: 03/05/2004
• Status: Active Grant

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Chingis Technology Corporation (MediaTek, Inc.)
• Inventors: Liu, Hsien-Wen, Wang, Alex, Shiau, Tzeng-Huei, Liu, I-Sheng, Chang, Shang-De Ted, Lin, Han-Chih
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US10/794,564
• Publication Number:
  US 20050199936A1
• Time in Patent Office: 865 Days
• Field of Search: 257314-316, 257/318, 257/326
• US Class Current: 257/315
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A single-poly two-transistor PMOS memory cell for multiple-time programming applications includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor all formed within a first n-well. A control plate for the floating gate transistor is formed in a second n-well. A single-poly two-transitor PMOS memory cell for one-time programming applications includes a PMOS floating gate transistor having a source formed as a p+ diffusion region in a single n-well. The source is adapted to also serve as control plate for the floating gate transistor.

Claims

1. A single-poly two-transistor (2T) PMOS memory cell, comprising:

a PMOS soled gate transistor having a drain and a source formed as separate p+ diffusion regions in a first n-well;

a PMOS floating gate transistor having a drain and a source formed as separate P+ diffusion regions in the n-well, wherein the p+ diffusion region that forms the floating gate transistor'"'"'s drain is the same p+ diffusion region that forms the select gate transistor'"'"'s source; and

a control plate for the PMOS floating gate transistor formed within a second n-well well, the second n-well being separated from the first n-well.

2. The 2T PMOS memory cell of claim 1, wherein an extension of a floating gate for the PMOS floating gate transistor overlays the separate n-well, the control plate being formed by that portion of the second n-well covered by the extension of the floating gate.

3. The 2T PMOS memory cell of claim 2, wherein the extension of the floating gate is doped n+ and the second n-well has an n-type type threshold adjust implant.

4. The 2T PMOS memory cell of claim 3, wherein the n-type doping of the extension of the floating gate and threshold adjust implant is such that their Fermi levels are substantially equal.

5. The 2T PMOS memory cell of claim 2, wherein the extension of a floating gate for overlaying the second n-well includes a digitated portion comprising finger extensions.

6. The 2T PMOS memory cell of claim 5, wherein the second n-well includes LDD implants between adjacent fingers of the digitated portion.

7. The 2T PMOS memory cell of claim 6, wherein the finger extensions are bounded by LDD spacers, the second n-well including an n+ diffusion region between adjacent finger extension'"'"'s LDD spacers.