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Nonvolatile memory solution using single-poly pFlash technology

  • US 7,078,761 B2
  • Filed: 03/05/2004
  • Issued: 07/18/2006
  • Est. Priority Date: 03/05/2004
  • Status: Active Grant
First Claim
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1. A single-poly two-transistor (2T) PMOS memory cell, comprising:

  • a PMOS soled gate transistor having a drain and a source formed as separate p+ diffusion regions in a first n-well;

    a PMOS floating gate transistor having a drain and a source formed as separate P+ diffusion regions in the n-well, wherein the p+ diffusion region that forms the floating gate transistor'"'"'s drain is the same p+ diffusion region that forms the select gate transistor'"'"'s source; and

    a control plate for the PMOS floating gate transistor formed within a second n-well well, the second n-well being separated from the first n-well.

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