Capacitance detecting circuit and method, and fingerprint sensor using the same

• US 7,078,918 B2
• Filed: 11/10/2004
• Issued: 07/18/2006
• Est. Priority Date: 11/25/2003
• Status: Active Grant

• Current Assignee: Synaptics Incorporated
• Original Assignee: ALPS Electric Company Limited (Alps Alpine Co., Ltd.)
• Inventors: Saito, Junichi, Umeda, Yuichi
• Primary Examiner(s): Nguyen, Vincent Q.
• Application Number:
  US10/986,505
• Publication Number:
  US 20050141263A1
• Time in Patent Office: 615 Days
• Field of Search: 324/679, 324/686, 382/124
• US Class Current: 324/679
• CPC Class Codes: G06F 3/04166 Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184
• CPC Class Codes: G06F 3/04182 Filtering of noise external to the device and not generated by digitiser components
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
• CPC Class Codes: G06V 40/1306 non-optical, e.g. ultrasonic or capacitive sensing

Abstract

In a capacitance detecting circuit, changes in capacitances at intersections between a plurality of row lines and a column line are detected as voltages. The capacitance detecting circuit includes a column-line driver for driving the column line. A code generator generates code having orthogonality in chronological order. A selection synthesizer selects a certain number of row lines from the plurality of row lines by using the code and synthesizes measured voltages at the intersections between the selected row lines and the driven column line so as to output the synthesized measured voltage. A decoding computation unit separates the measured voltages corresponding to the capacitances at the intersections by performing product sum computation between the synthesized measured voltage and the code.

Claims

1. A capacitance detecting circuit for detecting changes in capacitances at intersections between a plurality of row lines and a column line as voltages, comprising:

column-line driving means for driving the column line;

code generating means for generating code having orthogonality in chronological order;

selection synthesizing means for selecting a certain number of row lines from the plurality of row lines by using the code and for synthesizing measured voltages at the intersections between the selected row lines and the driven column line so as to output the synthesized measured voltage in chronological order; and

decoding computation means for separating the measured voltages corresponding to the capacitances at the intersections by performing product sum computation between the synthesized measured voltage and the code.

2. The capacitance detecting circuit according to claim 1, wherein the selection synthesizing means comprises:

row-line selection means for dividing the plurality of row lines into a first row line group and a second row line group based on the code and for synthesizing the measured voltages for each of the first row line group and the second row line group so as to output the measured voltages as a first synthesized measured voltage and a second synthesized measured voltage, respectively; and

differential amplifying means for differentially amplifying the first synthesized measured voltage and the second synthesized measured voltage so as to output a difference voltage between the first synthesized measured voltage and the second synthesized measured voltage corresponding to capacitances connected to the first row line group and the second row line group, respectively.

3. The capacitance detecting circuit according to claim 2, wherein the plurality of row lines are divided into a plurality of row line groups, each having a predetermined number of row lines, and

the selection synthesizing means selectively changes the plurality of row line groups at predetermined intervals in chronological order, and drives the selected row line group by dividing the row lines into the first row line group and the second row line group based on the code without driving the row lines of the unselected row line groups.

4. A fingerprint sensor comprising the capacitance detecting circuit set forth in claim 2.

5. The capacitance detecting circuit according to claim 3, wherein the row line group includes the number of row lines smaller than the number of bits of the code, and

the decoding computation means performs product sum computation by associating the row lines of the row line group with the bits at predetermined positions and by associating an imaginary row line with the remaining bit so as to decode the voltages corresponding to the capacitances at the intersections.

6. A fingerprint sensor comprising the capacitance detecting circuit set forth in claim 3.

7. The capacitance detecting circuit according to claim 1, wherein the code generating means generates PN code having autocorrelation, and sequentially shifts the order of a bit string of the PN code so as to output the PN code out of phase with each other in chronological order as the code.

8. The capacitance detecting circuit according to claim 1, wherein the code generating means generates Walsh orthogonal code having different orders of bit strings in chronological order so as to output the Walsh orthogonal code as the code.

9. The capacitance detecting circuit according to claim 1, wherein the capacitance detecting circuit is used for an area sensor in which the plurality of row lines and a plurality of column lines are disposed in a matrix to form intersections.

10. A fingerprint sensor comprising the capacitance detecting circuit set forth in claim 1.

11. A capacitance detecting method for detecting changes in capacitances at intersections between a plurality of row lines and a column line as voltages, comprising:

a column-line driving step of driving the column line;

a code generating step of generating code having orthogonality in chronological order;

a selection synthesizing step of selecting a certain number of row lines from the plurality of row lines by using the code and for synthesizing measured voltages at the intersections between the selected row lines and the driven column line so as to output the synthesized measured voltage in chronological order; and

a decoding computation step of separating the measured voltages corresponding to the capacitances at the intersections by performing product sum computation between the synthesized measured voltage and the code.