Method and system for filter tuning using a digital trim value

• US 7,078,960 B2
• Filed: 07/28/2003
• Issued: 07/18/2006
• Est. Priority Date: 07/28/2003
• Status: Active Grant

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: Microtune, Inc. (Qualcomm, Inc.)
• Inventors: Ezell, R. William
• Primary Examiner(s): Barnie, Rexford
• Assistant Examiner(s): Nguyen, Khai M.
• Application Number:
  US10/629,019
• Publication Number:
  US 20050024252A1
• Time in Patent Office: 1,086 Days
• Field of Search: 341/169, 327552-553
• US Class Current: 327/553
• CPC Class Codes: H03H 11/0472 Current or voltage controlled filters
• CPC Class Codes: H03H 2210/012 Centre frequency; Cut-off frequency
• CPC Class Codes: H03H 2210/021 Amplifier, e.g. transconductance amplifier
• CPC Class Codes: H03H 2210/033 Continuous
• CPC Class Codes: H03H 2210/036 Stepwise
• CPC Class Codes: H03H 2210/046 Master -slave
• CPC Class Codes: H03J 2200/07 Calibration of receivers, using quartz crystal oscillators as reference
• CPC Class Codes: H03J 2200/28 Automatic self-alignment of a receiver
• CPC Class Codes: H03J 2200/29 Self-calibration of a receiver

Abstract

A method for storing a result of a tuning process includes generating a first characteristic signal using a signal generator. The method also includes generating a second characteristic signal using a master circuit, wherein the master circuit generates the second characteristic signal in response to a current signal. The method further includes determining an adjustment to the current signal based at least in part upon the first and second characteristic signals, and storing a digital value representing the adjustment.

Claims

1. A method for storing a result of a tuning process, comprising:

a) generating a first characteristic signal;

b) generating a second characteristic signal in response to a current signal;

c) determining an adjustment to the current signal based at least in part upon the first and second characteristic signals;

d) storing, in a memory, a digital value representing the adjustment;

e) repeating elements a) through d) iteratively and updating the digital value stored in the memory after each iteration; and

f) stopping the iterative repetition upon performing a predetermined number of iterations.

2. The method of claim 1, wherein:

the digital value comprises a plurality of bits; and

the method further comprises storing the result of each iteration in a bit of the digital value.

3. The method of claim 1, wherein the adjustment to the current signal during a particular iteration is based on the last bit of the digital value stored.

4. The method of claim 1, wherein the first characteristic signal comprises a voltage measured across a reference capacitor of a signal generator and the second characteristic signal comprises a voltage measured across a capacitor of a master circuit.

5. The method of claim 4, wherein determining comprises comparing voltages across the respective capacitors when the reference capacitor reaches a predetermined voltage.

6. The method of claim 1, wherein:

the second characteristic signal is generated using a master circuit that is part of an integrated circuit; and

the first characteristic signal is generated by a signal generator that comprises;

an external reference capacitor; and

an external reference resistor.

7. The method of claim 1, wherein storing the digital value is performed even if circuitry used to complete the filter tuning process is powered down or disabled.

8. The method of claim 1, wherein the step of determining comprises:

generating a clock signal when the first characteristic signal reaches a predetermined voltage;

storing a data signal in response to the clock signal, the data signal indicating whether the second characteristic signal is greater than or less than the first characteristic signal.

9. The method of claim 8, wherein:

the digital value comprises a plurality of bits; and

the step of storing comprises storing the data signal in a bit of the digital value.

10. The method of claim 8, further comprising:

increasing the current signal if the data signal indicates that the second characteristic signal is less than the first characteristic signal; and

decreasing the current signal if the data signal indicates that the second characteristic signal is greater than the first characteristic signal.

11. The method of claim 1, further comprising tuning a filter using the stored digital value.

12. A tuning circuit, comprising:

a signal generator operable to generate a first characteristic signal;

a master circuit operable to receive a current signal and to generate a second characteristic signal in response to the current signal;

a controller operable to;

a) determine an adjustment to the current signal based at least in part upon the first and second characteristic signals;

b) store, in a memory, a digital value representing the adjustment;

c) repeat elements a) and b) iteratively and update the digital value stored in the memory after each iteration; and

a counter operable to maintain a count of a number of iterations completed by the controller, wherein the controller is further operable to stop the iterative repetition of the steps in response to the count reaching a predetermined number; and

the memory operable to store the digital values.

13. The circuit of claim 12, wherein:

the digital value comprises a plurality of bits; and

the controller is further operable to store the result of each iteration in a bit of the digital value.

14. The circuit of claim 12, wherein the adjustment to the current value during a particular iteration is based on the last bit stored in the digital value.

15. The circuit of claim 12, wherein the first characteristic signal comprises a voltage measured across a reference capacitor and the second characteristic signal comprises a voltage measured across a capacitor of the master circuit.

16. The circuit of claim 15, wherein the controller determines the adjustment based on a comparison of the voltages across the respective capacitors when the external reference capacitor reaches a predetermined voltage.

17. The circuit of claim 12, wherein:

the master circuit is part of an integrated circuit; and

the signal generator comprises;

an external reference capacitor; and

an external reference resistor.

18. The circuit of claim 12, wherein the memory continues to store the digital value even if one or more of the signal generator, master circuit, and the controller is powered down or disabled.

19. The circuit of claim 12, wherein:

the controller is further operable to receive a clock signal indicating that the first characteristic signal has reached a predetermined voltage; and

the controller is further operable to store a data signal in the memory in response to the clock signal, the data signal indicating whether the second characteristic signal is greater or less than the first characteristic signal.

20. The circuit of claim 19, wherein:

the digital value comprises a plurality of bits; and

the memory is further operable to store the data signal in a bit of the digital value.

21. The circuit of claim 19, wherein the controller is further operable to:

increase the current signal if the data signal indicates that the second characteristic signal is less than the first characteristic signal; and

decrease the current signal if the data signal indicates that the second characteristic signal is greater than the first characteristic signal.

22. The circuit of claim 12, further comprising a filter that is tuned using the stored digital value.

23. A circuit, comprising:

a first comparator operable to;

compare a first voltage across a first capacitor to a reference voltage; and

generate a signal when the first voltage reaches the reference voltage;

a second comparator operable to compare a second voltage measured across a second capacitor to a third voltage;

a counter operable to maintain a count of the number of signals generated by the first comparator;

a memory operable to store a digital value comprising a plurality of bits; and

a controller operable to receive the signal from the first comparator and, in response, to store the result of the comparison performed by the second comparator in a particular bit of the digital value identified by the count on the counter.

24. The circuit of claim 23, further comprising a reference current source coupled to the first capacitor and operable to charge the first capacitor.

25. The circuit of claim 23, further comprising a variable current source coupled to the second capacitor and operable to charge the second capacitor, wherein the amount of current produced by the variable current source is adjusted based on the result of the comparison performed by the second comparator.

26. The circuit of claim 23, wherein the value of the third voltage comprises the value of the reference voltage.

27. The circuit of claim 23, wherein the value of the third voltage comprises the value of the first voltage.

28. The circuit of claim 23, further comprising a filter that is tuned using the stored digital value.

29. A system, comprising:

means for generating a first characteristic signal;

means for generating a second characteristic signal in response to a current signal;

means for iteratively determining an adjustment to the current signal based at least in part upon the first and second characteristic signals;

means for storing a digital value representing the adjustment, wherein the means for storing is operable to update the digital value after each iteration;

means for counting a number of iterations performed by the means for determining the adjustment; and

means for stopping the iteration of the means for determining upon the means for determining performing a predetermined number of iterations.