Integrated PULSHI mode with shutdown

• US 7,078,963 B1
• Filed: 03/19/2004
• Issued: 07/18/2006
• Est. Priority Date: 03/21/2003
• Status: Expired due to Fees

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: D2Audio LLC (Renesas Electronics Corporation)
• Inventors: Attwood, Brian E., Andersen, Jack B.
• Primary Examiner(s): Smith, Zandra V.
• Assistant Examiner(s): NGUYEN, HIEU P
• Application Number:
  US10/805,592
• Time in Patent Office: 851 Days
• Field of Search: 330/10, 330/251, 330/207.A, 330/195
• US Class Current: 330/10
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 2200/351 Pulse width modulation being used in an amplifying circuit
• CPC Class Codes: H03F 2200/537 A transformer being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 3/217 Class D power amplifiers; Switching amplifiers
• CPC Class Codes: H03F 3/2171 with field-effect devices H03F3/2173 - H03F3/2178 take precedence
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation

Abstract

Systems and methods for controlling amplification of a pair of pulse width modulated signals. In one embodiment, a system comprises an audio amplifier which is configured to receive a pulse code modulated (PCM) input signal, convert this signal to a pulse width modulated (PWM) signal in a controller, and amplify the PWM signal in an output stage. The controller separates the PWM signal into a high-side signal and a low-side signal. The controller incorporates digitally programmable delays into the processing paths for each of the high-side and low-side signals. The high-side and low-side signals are separately provided to the output stage. The separate high-side and low-side signals can be used to individually control (e.g., turn off) the high-side and low-side transistors. Circuitry is included to generate a short low-side pulse when both transistors are turned off in order to drain the gate charge from the high-side transistor.

Claims

1. A system comprising:

a pulse width modulation (PWM) controller,

wherein the PWM controller provides a first output for a high-side PWM signal and a second output for a low-side PWM signal; and

output stage,

wherein the output stage is configured to receive the high-side signal from the first PWM controller output and the low-side signal from the second PWM controller output, and

wherein the high-side signal is coupled to a high-side transistor through a pulse transformer

wherein the output stage further comprises a third transistor, wherein the third transistor is coupled to receive the low-side signal and wherein the third transistor is configured to turn off the high-side transistor when the low-side signal is asserted.

2. The system of claim 1, wherein the low-side signal is coupled to the third transistor through one or more level shifting capacitors.

3. The system of claim 1, wherein the PWM controller is configured to provide a pulse at the second PWM controller output upon shutdown of the transistors.

4. The system of claim 1, wherein the low-side signal is coupled to a low-side transistor through one or more level shifting capacitors.

5. The system of claim 1, further comprising a high-side programmable delay unit configured to delay the high-side signal by a first programmable amount and a low side programmable delay unit configured to delay the low-side signal by a second programmable amount.

6. The system of claim 1, wherein the PWM controller is configured to produce a pulse as the high-side signal at the first PWM controller output.

7. The system of claim 5, wherein the high-side programmable delay unit and the low-side programmable delay unit are integrated into the PWM controller.

8. The system of claim 5, wherein the high-side programmable delay unit is digitally programmable to adjust the first programmable amount and the low-side programmable delay unit is digitally programmable to adjust the second programmable amount.

9. The system of claim 5, wherein the PWM controller is configured to adjust overlap of pulses of the high-side signal and the low-side signal by adjusting at least one of the first and second programmable amounts.

10. The system of claim 6, wherein the output stage further comprises a low-voltage driver, and wherein the low-voltage driver amplifies the pulse and transmits the amplified pulse to the pulse transformer.

11. An output stage for a PWM amplifier comprising:

a first input for a high-side PWM signal and a second input for a low-side PWM signal;

a first transistor coupled to receive the high-side PWM signal and a second transistor coupled to receive the low-side PWM signal;

a pulse transformer coupled between the first input and the first transistor; and

a third transistor coupled between the second input and the first transistor;

wherein when a pulse is received at the first input, the first transistor is turned on, and when a pulse is received at the second input, the second transistor is turned on and the first transistor is turned off.

12. The system of claim 11, wherein the low-ide signal is coupled to the third transistor through one or more level shifting capacitors.

13. The system of claim 11, wherein the PWM controller is configured to provide a pulse at the second PWM controller output upon shutdown of the transistors.

14. The system of claim 11, further comprising one or more level shifting capacitors coupled between the second input and the second and third transistors.