V.42bis standalone hardware accelerator and architecture of construction
First Claim
1. A method for on-chip processing of data, the method comprising:
- generating a plurality of data processing commands for data compression; and
encoding a first string of characters in one operating cycle utilizing said generated plurality of data processing commands for data compression,wherein said plurality of data processing commands and said first string of characters are stored in a single on-chip memory utilizing a character tree structure proceeding from at least one leaf node to at least one root node during said one operating cycle.
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Accused Products
Abstract
Methods and systems for on-chip processing of data are disclosed. Aspects of the method may include generating a plurality of data processing commands for data compression. A first string of characters may be encoded in one operating cycle utilizing the generated plurality of data processing commands for data compression. The plurality of data processing commands may comprise a branch command, a register moving command, a register setting command, a memory load command, a memory store command, and/or a register compare command. The generated plurality of data processing commands may be stored. At least a portion of the stored data processing commands may be decoded. The decoded portion of the stored data processing commands may be sequenced. The first string of characters may be acquired from a character space. The acquired first string of characters may be matched with at least one existing codeword.
23 Citations
36 Claims
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1. A method for on-chip processing of data, the method comprising:
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generating a plurality of data processing commands for data compression; and encoding a first string of characters in one operating cycle utilizing said generated plurality of data processing commands for data compression, wherein said plurality of data processing commands and said first string of characters are stored in a single on-chip memory utilizing a character tree structure proceeding from at least one leaf node to at least one root node during said one operating cycle. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A machine-readable storage having stored thereon, a computer program having at least one code section for on-chip processing of data, the at least one code section being executable by a machine for causing the machine to perform steps comprising:
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generating a plurality of data processing commands for data compression; and encoding a first string of characters in one operating cycle utilizing said generated plurality of data processing commands for data compression, wherein said plurality of data processing commands and said first string of characters are stored in a single on-chip memory utilizing a character tree structure proceeding from at least one leaf node to at least one root node during said one operating cycle. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A system for on-chip processing of data, the system comprising:
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an accelerator that generates a plurality of data processing commands for data compression; and said accelerator encodes a first string of characters in one operating cycle utilizing said generated plurality of data processing commands for data compression, wherein said plurality of data processing commands and said first string of characters are stored in a single on-chip memory utilizing a character tree structure proceeding from at least one leaf node to at least one root node during said one operating cycle. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36)
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Specification