System and method for cooperative operation of a processor and coprocessor

• US 7,079,147 B2
• Filed: 05/14/2003
• Issued: 07/18/2006
• Est. Priority Date: 05/14/2003
• Status: Active Grant

• Current Assignee: VeriSilicon Holdings Co., Ltd. (Verisilicon Microelectronics (Shanghai) Co. Ltd.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Chiang, Yetung P., Wichman, Shannon A., Trombetta, Ramon C.
• Primary Examiner(s): Tung, Kee M.
• Assistant Examiner(s): Richer, Aaron M.
• Application Number:
  US10/437,485
• Publication Number:
  US 20040227763A1
• Time in Patent Office: 1,161 Days
• Field of Search: 345/501, 345/503, 345/520, 345/522, 345/559, 375/240.16, 375/240.17, 375/240.24, 382/232, 382/236, 712/34, 712/203, 712/209, 725/105, 725/135
• US Class Current: 345/503
• CPC Class Codes: H04N 19/43 Hardware specially adapted for motion estimation or compensation
• CPC Class Codes: H04N 19/523 with sub-pixel accuracy
• CPC Class Codes: H04N 5/145 Movement estimation for video coding H04N19/51

Abstract

A disclosed coprocessor receives a user-defined command during execution of an instruction including the user-defined command, and performs a predetermined function in response to the user-defined command. The user-defined command includes multiple ordered bits having values assigned by a user. In one embodiment, the coprocessor includes logic coupled to receive the user-defined command and a datapath. The logic produces a control value in response to the user-defined command. The datapath receives data and the control value, and performs the predetermined function dependent upon the control value. In one embodiment, the predetermined function is a motion estimation function. Data processing systems are described including a processor coupled to the coprocessor. Another disclosed data processing system includes an arbiter coupled between a processor and multiple coprocessors. The arbiter receives the user-defined command, and provides the user-defined command to one of the coprocessors dependent upon the user-defined command.

Claims

1. A processor interface configured to couple a processor to a coprocessor and allow said processor to signal said coprocessor to operate in a selected one of a tightly-coupled mode and a loosely-coupled mode based on a received program instruction, wherein said coprocessor signals said processor interface to stall a pipeline of said processor when said coprocessor is in said tightly-coupled mode, and a result from said coprocessor is unavailable.

2. The processor interface as recited in claim 1, wherein said coprocessor provides an interrupt to said processor to signal availability of a result when said coprocessor interface is in said loosely-coupled mode.

3. The processor interface as recited in claim 1, wherein said coprocessor depends on said processor to provide data from a memory system when said coprocessor interface is in said tightly-coupled mode.

4. The processor interface as recited in claim 1, wherein said coprocessor directly accesses a memory system when said coprocessor interface is in said loosely-coupled mode.

5. The processor interface as recited in claim 1, wherein said coprocessor is configured to perform a motion estimation function.

6. The processor interface as recited in claim 1, wherein said processor interface couples a plurality of coprocessors to said processor.

7. A method of interfacing a processor to a coprocessor, wherein said processor signals said coprocessor to operate in a selected one of a tightly-coupled mode and a loosely-coupled mode based on a received program instruction, wherein said coprocessor signals said processor interface to stall a pipeline of said processor when said coprocessor is in said tightly-coupled mode, and a result from said coprocessor is unavailable.

8. The method as recited in claim 7, wherein said coprocessor provides an interrupt to said processor to signal availability of a result when said coprocessor interface is in said loosely-coupled mode.

9. The method as recited in claim 7, wherein said coprocessor depends on said processor to provide data from a memory system when said tightly-coupled mode is selected.

10. The method as recited in claim 7, wherein said coprocessor directly accesses a memory system when said loosely-coupled mode is selected.

11. The method as recited in claim 7, wherein said coprocessor is configured to perform a motion estimation function.

12. The method as recited in claim 7, wherein said processor interface couples a plurality of coprocessors to said processor.

13. A data processing system, comprising:

a processor;

a coprocessor; and

a processor interface configured to couple a processor to a coprocessor and allow said processor to signal said coprocessor to operate in a selected one of a tightly-coupled mode and a loosely-coupled mode based on a received program instruction, wherein said coprocessor signals said processor interface to stall a pipeline of said processor when said coprocessor is in said tightly-coupled mode, and a result from said coprocessor is unavailable.

14. The data processing system as recited in claim 13, wherein said coprocessor provides an interrupt to said processor to signal availability of a result when said coprocessor interface is in said loosely-coupled made.

15. The data processing system as recited in claim 13, further comprising a memory system, wherein said coprocessor depends on said processor to provide data from said memory system when said coprocessor interface is in said tightly-coupled mode.

16. The data processing system as recited in claim 13, further comprising a memory system, wherein said coprocessor directly accesses said memory system when said coprocessor interface is in said loosely-coupled mode.

17. The data processing system as recited in claim 13, wherein said coprocessor is configured to perform a motion estimation function.

18. The data processing system as recited in claim 13, wherein said processor interface couples a plurality of coprocessors to said processor.