Content addressable memory (CAM) device including match line sensing

• US 7,079,407 B1
• Filed: 10/18/2002
• Issued: 07/18/2006
• Est. Priority Date: 10/18/2002
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Netlogic Microsystems Incorporated (Broadcom, Inc.)
• Inventors: Dimitrelis, Dimitrios
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US10/273,684
• Time in Patent Office: 1,369 Days
• Field of Search: 365/49, 365/189.07
• US Class Current: 365/49.1
• CPC Class Codes: G11C 15/04 using semiconductor elements

Abstract

A content addressable memory (CAM) device that includes a plurality of CAM cells coupled to a match line to affect a voltage of the match line in response to data values of the CAM cells and comparand data being in a predetermined logical relationship, and a match detect circuit coupled to the match line and adapted to differentially compare the voltage of the match line with a fixed reference voltage and, in response, generate an output signal having two or more logical states corresponding to the states of the predetermined logical relationship between the data value and the comparand data.

Claims

1. A content addressable memory (CAM) device comprising:

a plurality of CAM cells coupled to a match line to affect a voltage of the match line in response to a comparison between data values of the CAM cells and comparand data; and

a match detect circuit coupled to the match line and coupled to receive a plurality of fixed reference voltages, the match detect circuitry including circuitry to compare the voltage of the match line with at least one of the plurality of fixed reference voltages and, in response, generate an output signal having two or more logical states according to whether the voltage of the match line exceeds the at least one of the plurality of fixed reference voltages.

2. The CAM device of claim 1, wherein the two logical states include a first logical state indicating that one or more of the data values does not match the comparand data of the match line and a second logical state indicating that the data values do match the comparand data of the match line.

3. The CAM device of claim 1, further comprising a pre-charge circuit coupled to pre-charge the voltage of the match line.

4. The CAM device of claim 1, wherein the match detect circuit includes a differential amplifier coupled to receive the match line signal at a first input and one of the plurality of fixed reference voltages at a second input.

5. The CAM device of claim 1, further comprising a reference circuit coupled to output the plurality of fixed reference voltages to the match detect circuit.

6. The CAM device of claim 1, further comprising circuitry to compare the voltage of the match line with each of the plurality of fixed reference voltages.

7. A content addressable memory (CAM) device comprising:

a plurality of CAM cells coupled to a match line to affect a voltage of the match line in response to a comparison between data values of the CAM cells and comparand data; and

means for receiving a plurality of fixed reference voltages, including means for comparing the voltage of the match line with at least one of the plurality of fixed reference voltages and, in response, generate an output signal having two or more logical states according to whether the voltage of the match line exceeds the at least one of the plurality of fixed reference voltages.

8. The CAM device of claim 7, further comprising means for generating the plurality of fixed reference voltages.

9. A content addressable memory (CAM) device comprising:

a sense amplifier circuit coupled to a match line having inputs to receive a match line signal and a plurality of reference voltages, and an output to provide an output signal having a first logical state representative of a first condition in which a voltage of the match line signal is greater than one of the plurality of reference voltages and a second logical state representative of a second condition in which a voltage of the match line signal is less than one of the plurality of reference voltages.

10. The CAM device of claim 9, further comprising a plurality of CAM cells coupled to the match line, and wherein the first condition represents a match between data of the CAM cells and comparand data, wherein the second condition represents a non-match between data and comparand data resulting from the compare operations.

11. The CAM device of claim 9, wherein the sense amplifier includes a differential amplifier coupled to receive the match line signal at the first input and coupled to receive the one of the plurality of reference voltages at the second input.

12. The CAM device of claim 9, further comprising a latching circuit coupled to the output of the sense amplifier circuit.

13. The CAM device of claim 9, further comprising a pre-charge circuit coupled to the match line and the first input of the sense amplifier circuit.

14. The CAM device of claim 9, wherein the sense amplifier circuit is configured to compare the voltage of the match line with each of the plurality of fixed reference voltages.

15. A method, comprising:

comparing comparand data with data values stored in a plurality of content addressable memory (CAM) cells to affect a voltage of a match line;

generating a plurality of fixed reference voltages; and

differentially sensing when the voltage of the match line is different than the one of the fixed reference voltages.

16. The method of claim 15, further comprising pre-charging the match line.

17. The method of claim 15, further comprising latching an output signal generated in response to the sensing.

18. The method of claim 15, wherein differentially sensing when the voltage of the match line is different than the one of the fixed reference voltages comprises comparing the voltage of the match line with each of the plurality of fixed reference voltages.

19. A method, comprising:

receiving a match line signal from a match line coupled to a plurality of content addressable memory (CAM) cells;

receiving a plurality of reference voltages that have respective fixed voltage values; and

,

generating an output signal having a first logical state representative of a first condition in which a voltage of the match line signal is greater than a first one of the plurality of reference voltages and a second logical state representative of a second condition in which a voltage of the match line signal is less than the first one of plurality of reference voltages.

20. The method of claim 19, further comprising comparing comparand data with data of the CAM cells.

21. The method of claim 19, wherein the generating comprises differentially sensing when the voltage of the match line signal is greater than the first one of the plurality of reference voltages and when the voltage of the match line signal is less than the first one of the plurality of reference voltages.

22. The method of claim 19, further comprising latching the output signal.

23. The method of claim 19, further comprising pre-charging the match line.

24. The method of claim 19, wherein generating the output signal comprises comparing the voltage of the match line with each of the plurality of fixed reference voltages.