Content addressable memory (CAM) device including match line sensing
First Claim
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1. A content addressable memory (CAM) device comprising:
- a plurality of CAM cells coupled to a match line to affect a voltage of the match line in response to a comparison between data values of the CAM cells and comparand data; and
a match detect circuit coupled to the match line and coupled to receive a plurality of fixed reference voltages, the match detect circuitry including circuitry to compare the voltage of the match line with at least one of the plurality of fixed reference voltages and, in response, generate an output signal having two or more logical states according to whether the voltage of the match line exceeds the at least one of the plurality of fixed reference voltages.
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Abstract
A content addressable memory (CAM) device that includes a plurality of CAM cells coupled to a match line to affect a voltage of the match line in response to data values of the CAM cells and comparand data being in a predetermined logical relationship, and a match detect circuit coupled to the match line and adapted to differentially compare the voltage of the match line with a fixed reference voltage and, in response, generate an output signal having two or more logical states corresponding to the states of the predetermined logical relationship between the data value and the comparand data.
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Citations
24 Claims
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1. A content addressable memory (CAM) device comprising:
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a plurality of CAM cells coupled to a match line to affect a voltage of the match line in response to a comparison between data values of the CAM cells and comparand data; and a match detect circuit coupled to the match line and coupled to receive a plurality of fixed reference voltages, the match detect circuitry including circuitry to compare the voltage of the match line with at least one of the plurality of fixed reference voltages and, in response, generate an output signal having two or more logical states according to whether the voltage of the match line exceeds the at least one of the plurality of fixed reference voltages. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A content addressable memory (CAM) device comprising:
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a plurality of CAM cells coupled to a match line to affect a voltage of the match line in response to a comparison between data values of the CAM cells and comparand data; and means for receiving a plurality of fixed reference voltages, including means for comparing the voltage of the match line with at least one of the plurality of fixed reference voltages and, in response, generate an output signal having two or more logical states according to whether the voltage of the match line exceeds the at least one of the plurality of fixed reference voltages. - View Dependent Claims (8)
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9. A content addressable memory (CAM) device comprising:
a sense amplifier circuit coupled to a match line having inputs to receive a match line signal and a plurality of reference voltages, and an output to provide an output signal having a first logical state representative of a first condition in which a voltage of the match line signal is greater than one of the plurality of reference voltages and a second logical state representative of a second condition in which a voltage of the match line signal is less than one of the plurality of reference voltages. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A method, comprising:
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comparing comparand data with data values stored in a plurality of content addressable memory (CAM) cells to affect a voltage of a match line; generating a plurality of fixed reference voltages; and differentially sensing when the voltage of the match line is different than the one of the fixed reference voltages. - View Dependent Claims (16, 17, 18)
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19. A method, comprising:
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receiving a match line signal from a match line coupled to a plurality of content addressable memory (CAM) cells; receiving a plurality of reference voltages that have respective fixed voltage values; and
,generating an output signal having a first logical state representative of a first condition in which a voltage of the match line signal is greater than a first one of the plurality of reference voltages and a second logical state representative of a second condition in which a voltage of the match line signal is less than the first one of plurality of reference voltages. - View Dependent Claims (20, 21, 22, 23, 24)
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Specification