Complex phase-locked loop demodulator for low-IF and zero-IF radio receivers

• US 7,079,598 B2
• Filed: 07/15/2004
• Issued: 07/18/2006
• Est. Priority Date: 10/04/1999
• Status: Expired due to Term

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Riley, Thomas, Birkett, Neil, Filiol, Norm
• Primary Examiner(s): Fan, Chieh M.
• Assistant Examiner(s): PUENTE, EVA YI ZHENG
• Application Number:
  US10/891,586
• Publication Number:
  US 20040247050A1
• Time in Patent Office: 733 Days
• Field of Search: 375/327, 375/296, 375/295, 375/300, 342/357, 329/336
• US Class Current: 375/327
• CPC Class Codes: H03D 3/245 using at least twophase detectors in the loop H03D3/244 takes precedence; in general H03L7/087
• CPC Class Codes: H04L 27/3836 in which the carrier is recovered using the received modulated signal or the received IF signal, e.g. by detecting a pilot or by frequency multiplication

Abstract

A digital demodulator which coherently demodulates a low-IF or zero-IF complex signal using a complex-valued phase-locked loop (CPPL). The CPPL includes a numerical controlled oscillator, four multipliers and two combiners to provide independent phase/frequency and amplitude outputs. The CPLL exhibits in first order PLL dynamics without a loop filter in the feedback loop to the NCO. However a filter with one or more poles may be included in the feedback circuit to exhibit 2^nd or higher order PLL dynamics. The CPLL allows coherent demodulation of extremely low FM modulation indexes whereby the incoming frequency drift may be larger than the frequency deviation. It can also be used to coherently demodulate signals which have combined amplitude and phase characteristics.

Claims

1. A complex demodulator for demodulating an RF signal converted to digital I and Q IF signals, the complex demodulator comprising:

a phase output node;

an amplitude output node;

a numerically controlled oscillator (NCO) for generating first and second NCO output signals in quadrature centred at the IF frequency;

a first digital multiplier having a first input for receiving the digital I IF signal, a second input for receiving the first NCO output signal and an output for produce an output signal;

a second digital multiplier having a first input for receiving the digital Q IF signal, a second input for receiving the second NCO output signal and an output for produce an output;

a difference combiner for processing the outputs of the first and second digital multipliers to provide a phase signal at the phase output node, the phase signal being coupled to the NCO through a feedback loop to control the NCO frequency, the feedback loop exhibiting a first order loop characteristic in combination with the NCO; and

a circuit for processing the digital I IF signal and the digital Q IF signal based on the first and second NCO output signals to provide an amplitude signal at the amplitude output node, the circuit including a third digital multiplier having a first input for receiving the digital I IF signal, a second input for receiving the second NCO output signal and an output for produce an output signal;

a fourth digital multiplier having a first input for receiving the digital Q IF signal, a second input for receiving the first NCO output signal and an output for produce an output signal; and

a sum combiner coupled to the outputs of the third and fourth digital multipliers for providing the amplitude signal at its output.

2. A complex demodulator as claimed in claim 1, wherein one of the first and second NCO output signals is a sine signal, and the other is a cosine signal.

3. A complex demodulator as claimed in claim 1, wherein the demodulator is capable of demodulating a low-IF signal and/or a zero-IF signal.

4. A complex demodulator for demodulating an RF signal converted to digital I and Q IF signals, the complex demodulator comprising:

a numerically controlled oscillator (NCO) for generating first and second NCO output signals in quadrature centred at the IF frequency;

a first digital multiplier having a first input for receiving the digital I IF signal, a second input for receiving the first NCO output signal and an output for produce an output signal;

a second digital multiplier having a first Input for receiving the digital Q IF signal, a second input for receiving the second NCO output signal and an output for produce an output signal;

a difference combiner coupled to the outputs of the first and second digital multipliers for providing a phase signal at its output, the phase signal being coupled to the NCO through a feedback loop to control the NCO frequency, the feedback loop exhibiting a first order loop characteristic in combination with the NCO; and

a circuit for processing the digital I IF signal and the digital Q IF signal based on the first and second NCO output signals to provide an amplitude signal, the circuit including;

a third digital multiplier having a first input for receiving the digital I IF signal, a second input for receiving the second NCO output signal and an output for produce an output signal;

a fourth digital multiplier having a first input for receiving the digital Q IF signal, a second input for receiving the first NCO output signal and an output for produce an output signal; and

a sum combiner coupled to the outputs of the third and fourth digital multipliers for providing the amplitude signal at its output.

5. A complex demodulator as claimed in claim 4, wherein one of the first and second NCO output signals is a sine signal, and the other is a cosine signal.

6. A complex demodulator as claimed in claim 4, wherein the demodulator is capable of demodulating a low-IF signal and/or a zero-IF signal.