Apparatus and method for using training sequences to estimate timing error in a digital signal receiver

• US 7,079,613 B2
• Filed: 10/25/2001
• Issued: 07/18/2006
• Est. Priority Date: 10/25/2001
• Status: Expired due to Fees

• Current Assignee: Funai Electric Co., Ltd.
• Original Assignee: Koninklijke Philips N.V.
• Inventors: Birru, Dagnachew
• Primary Examiner(s): Burd, Kevin
• Assistant Examiner(s): TORRES, JUAN A
• Application Number:
  US10/144,820
• Publication Number:
  US 20030081700A1
• Time in Patent Office: 1,727 Days
• Field of Search: 375/354, 375/368, 375/365, 375/366, 327/141
• US Class Current: 375/354
• CPC Class Codes: H04L 7/027 extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
• CPC Class Codes: H04L 7/041 using special codes as synchronising signal
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/44209 Monitoring of downstream path of the transmission network originating from a server, e.g. bandwidth variations of a wireless network arrangements for maintenance or administration in data switching networks involving bandwidth and capacity management H04L41/0896
• CPC Class Codes: H04N 5/04 Synchronising for television systems using pulse code modulation H04N7/56

Abstract

An apparatus and method is disclosed for estimating timing error in a digital signal receiver from a difference between an arrival time of a first training sequence and an arrival time of a second training sequence in the digital signal receiver. Time domain representations of the timing sequence data are converted into frequency domain representations and used to calculate a complex cross power spectrum. The timing error is obtained by determining an average phase of the complex cross power spectrum. The timing error is then used to calculate an accurate value for the clock rate of the digital signal transmitter.

Claims

1. An apparatus for determining an estimate of timing error in a digital signal receiver, said apparatus comprising a timing error controller that is capable of determining said estimate of timing error from a difference between an arrival time of a first training sequence and an arrival time of a second training sequence in said digital signal receiver, wherein said timing error controller is capable of extracting y₁ data around said first training sequence received at time t₁ where said y₁ data is represented by:

y₁(t)=Σ

a_kh₁(t−

kT)+e₁(t)

where a_k represents said training sequence, h₁(t) represents a channel impulse response at time t₁, e₁(t) represents an error term, and T represents a clock period of a transmitter; and

wherein said timing error controller is capable of sampling said y₁ data at a rate T₂ that is approximately equal to said value T of said clock period of said transmitter to obtain sampled y₁ data represented by;

y₁(nT₂)=Σ

a_kh₁(nT₂−

kT)+e₁(nT₂).

2. An apparatus as claimed in claim 1 wherein said timing error controller is capable of calculating an arrival time t₂ of said second training sequence, and capable of extracting y₂ data around said second training sequence received at time t₂ where said y₂ data is represented by:

y₂(nT₂)=Σ

a_kh₂(nT₂−

kT−

τ

)+e₂(nT₂)

where a_k represents said training sequence, h₂(t) represents a channel impulse response at time t₂, e₂(nT₂) represents an error term, T represents a clock period of said transmitter, and τ

represents said timing error.

3. An apparatus as claimed in claim 2 wherein said timing error controller is capable of obtaining said y₂(nT₂) data in terms of said channel impulse response h₁(t) at time t₁, where said y₂(nT₂) data is represented by:

y₂(nT₂)=Σ

a_kh₁(nT₂−

kT−

τ

)+e₃(nT₂)

where e₃(nT₂) represents an error term that is equal to e₂(nT₂) plus Δ

h(t){circle around (x)}a_k where Δ

h(t) is a difference between h₁(t) and h₂(t), and where {circle around (x)} represents a convolution operation.

4. An apparatus as claimed in claim 3 wherein said timing error controller is capable of converting a time domain representation of y₁(nT₂)=Σ

a_kh₁(nT₂−

kT)+e₁(nT₂) to a frequency domain representation Y₁(e^jω

)=P(e^jω

)+E₁(e^jω

) where P(e^jω

) is a frequency domain representation of Σ

a_kh₁(nT₂−

kT) and where E₁(e^jω

) is a frequency domain representation of the term e₁(nT₂); and

where said timing error controller is capable of converting a time domain representation of y₂(nT₂)=Σ

a_kh₁(nT₂−

kT−

τ

)+e₃(nT₂) to a frequency domain representation y₂(e^jω

)=P(e^jω

)e<sup>jω

τ</sup>

+E₃(e^jω

) where P(e^jω

)e<sup>jω

τ</sup>

is a frequency domain representation of Σ

a_kh₁(nT₂−

kT−

τ

) and where E₃(e^jω

) is a frequency domain representation of the term e₃(nT₂).

5. An apparatus as claimed in claim 4 wherein said timing error controller is capable of multiplying said frequency domain representation Y₁(e^jω

) by a complex conjugate of said frequency domain representation Y₂(e^jω

) to calculate a complex cross power spectrum equal to;

Y₁(e^jω

)Y₂(e<sup>−

jω</sup>

)=|P(e^jω

)|²e<sup>−

jω</sup>

τ

+E₄(e^jω

)

where E₄(e^jω

) is a frequency domain representation of terms that are functions of e^jω

.

6. An apparatus as claimed in claim 5 wherein said timing error controller is capable of determining a value of said timing error τ

by determining an average phase of said complex cross power spectrum.

7. An apparatus as claimed in claim 6 wherein said timing error controller is capable of determining said value of said timing error τ

by finding an average of a phase of each frequency bin in an N-point Fast Fourier Transform (FFT) unit that calculates said complex cross power spectrum Y(k) by calculating;

8. An apparatus as claimed in claim 6 wherein said timing error controller is capable of determining said value of said timing error τ

by finding an average of a phase of each frequency bin in an N-point Fast Fourier Transform (FFT) unit that calculates said complex cross power spectrum Y(k) by calculating;

9. An apparatus as claimed in claim 6 wherein said timing error controller is capable of determining a value T of said transmitter clock period using:

τ

=MT−

MT₂=M(T−

T₂) where said value of said timing error τ

is known, and where M represents a known number of symbols between said first training sequence and said second training sequence, and where T₂ represents a known value of an approximate value of said transmitter clock period T.

10. A digital receiver system comprising an apparatus for determining an estimate of timing error in a digital signal receiver of said digital receiver system, said apparatus comprising a timing error controller that is capable of determining said estimate of timing error from a difference between an arrival time of a first training sequence and an arrival time of a second training sequence in said digital signal receiver, wherein said timing error controller is capable of extracting y₁ data around said first training sequence received at time t₁ where said y₁ data is represented by:

y₁(t)=Σ

a_kh₁(t−

kT)+e₁(t)

where a_k represents said training sequence, h₁(t) represents a channel impulse response at time t₁, e₁(t) represents an error term, and T represents a clock period of a transmitter; and

wherein said timing error controller is capable of sampling said y₁ data at a rate T₂ that is approximately equal to said value T of said clock period of said transmitter to obtain sampled y₁ data represented by;

y₁(nT₂)=Σ

a_kh₁(nT₂−

kT)+e₁(nT₂).

11. A digital receiver system as claimed in claim 10 wherein said timing error controller is capable of calculating an arrival time t₂ of said second training sequence, and capable of extracting y₂ data around said second training sequence received at time t₂ where said y₂ data is represented by:

y₂(nT₂)=Σ

a_kh₂(nT₂−

kT−

τ

)+e₂(nT₂)

where a_k represents said training sequence, h₂(t) represents a channel impulse response at time t₂, e₂(nT₂) represents an error term, T represents a clock period of said transmitter, and τ

represents said timing error.

12. A digital receiver system as claimed in claim 11 wherein said timing error controller is capable of obtaining said y₂(nT₂) data in terms of said channel impulse response h₁(t) at time t₁, where said y₂(nT₂) data is represented by:

y₂(nT₂)=Σ

a_kh₁(nT₂−

kT−

τ

)+e₃(nT₂)

where e₃(nT₂) represents an error term that is equal to e₂(nT₂) plus Δ

h(t){circle around (x)}a_k where Δ

h(t) is a difference between h₁(t) and h₂(t), and where {circle around (x)} represents a convolution operation.

13. A digital receiver system as claimed in claim 12 wherein said timing error controller is capable of converting a time domain representation of y₁(nT₂)=Σ

a_kh₁(nT₂−

kT)+e₁(nT₂) to a frequency domain representation Y₁(e^jω

)=P(e^jω

)+E₁(e^jω

) where P(e^jω

) is a frequency domain representation of Σ

a_kh₁(nT₂−

kT) and where E₁(e^jω

) is a frequency domain representation of the term e₁(nT₂); and

where said timing error controller is capable of converting a time domain representation of y₂(nT₂)=Σ

a_kh₁(nT₂−

kT−

τ

)+e₃(nT₂) to a frequency domain representation Y₂(e^jω

)=P(e^jω

)e<sup>jω

τ</sup>

+E₃(e^jω

) where P(e^jω

)e<sup>jω

τ</sup>

is a frequency domain representation of Σ

a_kh₁(nT₂−

kT−

τ

) and where E₃(e^jω

) is a frequency domain representation of the term e₃(nT₂).

14. A digital receiver system as claimed in claim 13 wherein said timing error controller is capable of multiplying said frequency domain representation Y₁(e^jω

) by a complex conjugate of said frequency domain representation Y₂(e^jω

) to calculate a complex cross power spectrum equal to;

Y₁(e^jω

)Y₂(e<sup>−

jω</sup>

)=|P(e^jω

)|²e<sup>−

jω</sup>

+E₄(e^jω

)

where E₄(e^jω

) is a frequency domain representation of terms that are functions of e^jω

.

15. A digital receiver system as claimed in claim 14 wherein said timing error controller is capable of determining a value of said timing error τ

by determining an average phase of said complex cross power spectrum.

16. A digital receiver system as claimed in claim 15 wherein said timing error controller is capable of determining said value of said timing error τ

by finding an average of a phase of each frequency bin in an N-point Fast Fourier Transform (FFT) unit that calculates said complex cross power spectrum Y(k) by calculating;

17. A digital receiver system as claimed in claim 15 wherein said timing error controller is capable of determining said value of said timing error τ

by finding an average of a phase of each frequency bin in an N-point Fast Fourier Transform (FFT) unit that calculates said complex cross power spectrum Y(k) by calculating;

18. A digital receiver system as claimed in claim 15 wherein said timing error controller is capable of determining a value T of said transmitter clock period using:

τ

=MT−

MT₂=M(T−

T₂) where said value of said timing error τ

is known, and where M represents a known number of symbols between said first training sequence and said second training sequence, and where T₂ represents a known value of an approximate value of said transmitter clock period T.

19. A method for determining an estimate of timing error in a digital signal receiver, said method comprising the step of:

determining said estimate of timing error from a difference between an arrival time of a first training sequence and an arrival time of a second training sequence in said digital signal receiver, wherein said step of determining said estimate of timing error comprises the steps of;

extracting y₁ data around said first training sequence received at time t₁ where said y₁ data is represented by;

y₁(t)=Σ

a_kh₁(t−

kT)+e₁(t)

where a_k represents said training sequence, h₁(t) represents a channel impulse response at time t₁, e₁(t) represents an error term, and T represents a clock period of a transmitter; and

sampling said y₁ data at a rate T₂ that is approximately equal to said value T of said clock period of said transmitter to obtain sampled y₁ data represented by;

y₁(nT₂)=Σ

a_kh₁(nT₂−

kT)+e₁(nT₂).

20. A method as claimed in claim 19 further comprising the steps of:

calculating an arrival time t₂ of said second training sequence; and

extracting y₂ data around said second training sequence received at time t₂ where said y₂ data is represented by;

y₂(nT₂)=Σ

a_kh₂(nT₂−

kT−

τ

)+e₂(nT₂)

where a_k represents said training sequence, h₂(t) represents a channel impulse response at time t₂, e₂(nT₂) represents an error term, T represents a clock period of said transmitter, and τ

represents said timing error.

21. A method as claimed in claim 20 further comprising the step of:

obtaining said y₂(nT₂) data in terms of said channel impulse response h₁(t) at time t₁, where said y₂(nT₂) data is represented by;

y₂(nT₂)=Σ

a_kh₁(nT₂−

kT−

τ

)+e₃(nT₂)

where e₃(nT₂) represents an error term that is equal to e₂(nT₂) plus Δ

h(t){circle around (x)}a_k where Δ

h(t) is a difference between h₁(t) and h₂(t), and where {circle around (x)} represents a convolution operation.

22. A method as claimed in claim 21 further comprising the steps of:

converting a time domain representation of y₁(nT₂)=Σ

a_kh₁(nT₂−

kT)+e₁(nT₂) to a frequency domain representation Y₁(e^jω

)=P(e^jω

)+E₁(e^jω

) where P(e^jω

) is a frequency domain representation of Σ

a_kh₁(nT₂−

kT) and where E₁(e^jω

) is a frequency domain representation of the term e₁(nT₂); and

converting a time domain representation of y₂(nT₂)=Σ

a_kh₁(nT₂−

kT−

τ

)+e₃(nT₂) to a frequency domain representation Y₂(e^jω

)=P(e^jω

)e<sup>jω

τ</sup>

+E₃(e^jω

) where P(e^jω

)e<sup>jω

τ</sup>

is a frequency domain representation of Σ

a_kh₁(nT₂−

kT−

τ

) and where E₃(e^jω

) is a frequency domain representation of the term e₃(nT₂).

23. A method as claimed in claim 22 further comprising the step of:

multiplying said frequency domain representation Y₁(e^jω

) by a complex conjugate of said frequency domain representation Y₂(e^jω

) to calculate a complex cross power spectrum equal to;

Y₁(e^jω

)Y₂(e<sup>−

jω</sup>

)=|P(e^jω

)|²e<sup>−

jω

τ</sup>

+E₄(e^jω

)

where E₄(e^jω

) is a frequency domain representation of terms that are functions of e^jω

.

24. A method as claimed in claim 23 further comprising the step of:

determining a value of said timing error τ

by determining an average phase of said complex cross power spectrum.

25. A method as claimed in claim 24 wherein said step of determining a value of said timing error τ

comprises the step of;

finding an average of a phase of each frequency bin in an N-point Fast Fourier Transform (FFT) unit that calculates said complex cross power spectrum Y(k) by calculating;

26. A method as claimed in claim 24 wherein said step of determining a value of said timing error τ

comprises the step of;

finding an average of a phase of each frequency bin in an N-point Fast Fourier Transform (FFT) unit that calculates said complex cross power spectrum Y(k) by calculating;

27. A method as claimed in claim 24 further comprising the step of:

determining a value T of said transmitter clock period using;

τ

=MT−

MT₂=M(T−

T₂) where said value of said timing error τ

is known, and where M represents a known number of symbols between said first training sequence and said second training sequence, and where T₂ represents a known value of an approximate value of said transmitter clock period T.

28. A computer executable process steps, stored on a computer readable storage medium, for determining an estimate of timing error in a digital signal receiver comprising the step of:

determining said estimate of timing error from a difference between an arrival time of a first training sequence and an arrival time of a second training sequence in said digital signal receiver, wherein said step of determining said estimate of timing error comprises the steps of;

extracting y₁ data around said first training sequence received at time t₁ where said y₁ data is represented by;

y₁(t)=Σ

a_kh₁(t−

kT)+e₁(t)

where a_k represents said training sequence, h₁(t) represents a channel impulse response at time t₁, e₁(t) represents an error term, and T represents a clock period of a transmitter; and

sampling said y₁ data at a rate T₂ that is approximately equal to said value T of said clock period of said transmitter to obtain sampled y₁ data represented by;

y₁(nT₂)=Σ

a_kh₁(nT₂−

kT)+e₁(nT₂).

29. The computer executable process steps, stored on a computer readable medium, as claimed in claim 28 further comprising the steps of:

calculating an arrival time t₂ of said second training sequence; and

extracting y₂ data around said second training sequence received at time t₂ where said y₂ data is represented by;

y₂(nT₂)=Σ

a_kh₂(nT₂−

kT−

τ

)+e₂(nT₂)

where a_k represents said training sequence, h₂(t) represents a channel impulse response at time t₂, e₂(nT₂) represents an error term, T represents a clock period of said transmitter, and τ

represents said timing error.

30. The computer executable process steps, stored on a computer readable medium, as claimed in claim 29 further comprising the step of:

obtaining said y₂(nT₂) data in terms of said channel impulse response h₁(t) at time t₁, where said y₂(nT₂) data is represented by;

y₂(nT₂)=Σ

a_kh₁(nT₂−

kT−

τ

)+e₃(nT₂)

where e₃(nT₂) represents an error term that is equal to e₂(nT₂) plus Δ

h(t){circle around (x)}a_k where Δ

h(t) is a difference between h₁(t) and h₂(t), and where {circle around (x)} represents a convolution operation.

31. The computer executable process steps, stored on a computer readable medium, as claimed in claim 30 further comprising the steps of:

converting a time domain representation of y₁(nT₂)=Σ

a_kh₁(nT₂−

kT)+e₁(nT₂) to a frequency domain representation Y₁(e^jω

)=P(e^jω

)+E₁(e^jω

) where P(e^jω

) is a frequency domain representation of Σ

a_kh₁(nT₂−

kT) and where E₁(e^jω

) is a frequency domain representation of the term e₁(nT₂); and

converting a time domain representation of y₂(nT₂)=Σ

a_kh₁(nT₂−

kT−

τ

)+e₃(nT₂) to a frequency domain representation Y₂(e^jω

)=P(e^jω

)e<sup>jω

τ</sup>

+E₃(e^jω

) where P(e^jω

)e<sup>jω

τ</sup>

is a frequency domain representation of Σ

a_kh₁(nT₂−

kT−

τ

) and where E₃(e^jω

) is a frequency domain representation of the term e₃(nT₂).

32. The computer executable process steps, stored on a computer readable medium, as claimed in claim 31 further comprising the step of:

multiplying said frequency domain representation Y₁(e^jω

) by a complex conjugate of said frequency domain representation Y₂(e^jω

) to calculate a complex cross power spectrum equal to;

Y₁(e^jω

)Y₂(e<sup>−

jω</sup>

)=|P(e^jω

)|²e<sup>−

jω

τ</sup>

+E₄(e^jω

)

where E₄(e^jω

) is a frequency domain representation of terms that are functions of e^jω

.

33. The computer executable process steps, stored on a computer readable medium, as claimed in claim 32 further comprising the step of:

determining a value of said timing error τ

by determining an average phase of said complex cross power spectrum.

34. The computer executable process steps, stored on a computer readable medium, as claimed in claim 33 wherein said step of determining a value of said timing error τ

comprises the step of;

finding an average of a phase of each frequency bin in an N-point Fast Fourier Transform (FFT) unit that calculates said complex cross power spectrum Y(k) by calculating;

35. The computer executable process steps, stored on a computer readable medium, as claimed in claim 33 wherein said step of determining a value of said timing error τ

comprises the step of;

finding an average of a phase of each frequency bin in an N-point Fast Fourier Transform (FFT) unit that calculates said complex cross power spectrum Y(k) by calculating;

36. The computer executable process steps, stored on a computer readable medium, as claimed in claim 33 further comprising the step of:

determining a value T of said transmitter clock period using;

τ

=MT−

MT₂=M(T−

T₂) where said value of said timing error τ

is known, and where M represents a known number of symbols between said first training sequence and said second training sequence, and where T₂ represents a known value of an approximate value of said transmitter clock period T.