System for monitoring a period of an operation clock signal of a CPU and stopping operations of the CPU when the period is out of a predetermined allowable range

• US 7,080,001 B2
• Filed: 02/26/2003
• Issued: 07/18/2006
• Est. Priority Date: 03/29/2002
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi ULSI Systems Company Limited (Hitachi, Ltd.), Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Shinohara, Shigeru, Moriyama, Naokatsu
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): CONNOLLY, MARK A
• Application Number:
  US10/372,970
• Publication Number:
  US 20040117693A1
• Time in Patent Office: 1,238 Days
• Field of Search: 713/600, 324/85, 702/117, 726/34
• US Class Current: 713/600
• CPC Class Codes: G06F 21/55 Detecting local intrusion or implementing counter-measures
• CPC Class Codes: G06F 21/755 with measures against power attack
• CPC Class Codes: G06F 21/77 in smart cards

Abstract

There is provided a technology for preventing disabling of function of a clock monitoring circuit by a hacker in a microcomputer for IC card provided with a clock monitoring circuit as a countermeasure for a hacker. In the microcomputer for IC card provided with the clock monitoring circuit, the clock monitoring circuit is given the function to perform the detecting operation twice during one cycle, namely at the timings of rise and fall of the clock.

Claims

1. A data processing system comprising:

a central processing unit (CPU);

a memory;

an interface for transmitting and receiving data to and from external devices;

a bus for connecting said CPU, memory, and interface; and

a clock monitoring circuit for monitoring period of an operation clock signal of said CPU to stop operations of said CPU when the period of said operation clock signal goes out of a predetermined allowable range,

wherein said clock monitoring circuit includes;

a first pulse width detecting circuit for generating a first voltage depending on a pulse width of said operation clock signal;

a discriminating circuit for discriminating the first voltage generated by said first pulse width detecting circuit with a predetermined threshold voltage; and

a control circuit for detecting an output of said discriminating circuit in response to rise and fall of said clock signal and generating a signal to stop the operations of said CPU based on a result of detection of said output; and

wherein said clock monitoring circuit includes a logical inverting circuit for inverting logic of outputs of said discriminating circuit, and said first pulse width detecting circuit includes a first flip-flop circuit for latching outputs of said discriminating circuit in a timing of rise or fall of the clock signal and a second flip-flop circuit for latching outputs of said logical inverting circuit in the timing of fall or rise of the clock signal, and

wherein said signal generated by said control circuit is a reset signal for resetting operations of said CPU.

2. A data processing system according to claim 1,

wherein said control circuit further includes a third flip-flop circuit for latching an output of said first flip-flop circuit in the timing of fall or rise of the clock signal and a fourth flip-flop circuit for latching an output of said second flip-flop circuit in the timing of rise or fall of the clock signal to generate said reset signal based on the result of logical product of outputs of said third and fourth flip-flop circuits.

3. A data processing system according to claim 2, further comprising:

a second pulse width detecting circuit for generating a second voltage depending on a pulse width of signal in the inverted phase of said clock signal;

a second discriminating circuit for discriminating the second voltage generated by said second pulse width detecting circuit with a predetermined threshold voltage level; and

a second control circuit for respectively detecting an output of said second discriminating circuit in the timings of fall and rise of said clock signal.

4. A data processing system according to claim 3,

wherein said reset signal is generated based on a logical product of output of said control circuit and output of said second control circuit.

5. A data processing system formed on a semiconductor chip, comprising:

a central processing unit (CPU);

a memory;

an interface for transmitting and receiving data to and from external devices;

a bus for connecting said CPU, memory, and interface;

a clock monitoring circuit for monitoring period of an operation clock signal of said CPU to stop operation of said CPU when the period of said clock signal goes out of a predetermined allowable range;

a plurality of signal lines closely allocated to each other on said semiconductor chip to cover at least an upper part of said clock circuit;

AC signal generating circuits connected to first terminals of a plurality of said signal lines to generate AC signals respectively to a plurality of said signal lines;

signal detecting circuits connected to second terminals of a plurality of said signal lines to detect said AC signals; and

a control circuit for stopping operation of said CPU when said signal detecting circuits do not detect said AC signals,

wherein said clock monitoring circuit includes;

a pulse first width detecting circuit for generating a voltage depending on the pulse width of said clock signal;

a discriminating circuit for discriminating the voltage generated by said first pulse width detecting circuit with a predetermined threshold value;

a control circuit for detecting an output of said discriminating circuit in a timing of rise or fall of said clock signal and generating a signal to stop operation of said CPU based on a result of detecton of said output, and

wherein said clock monitoring circuit includes a logical inverting circuit for inverting logic of outputs of said discriminating circuit, and said first pulse width detecting circuit includes a first flip-flop circuit for latching outputs of said discriminating circuit in a timing of rise or fall of said clock signal and a second flip-flop circuit for latching outputs of said logical inverting circuit in the timing of fall or rise of the clock signal, and

wherein said signal generated by said control circuit is a reset signal for resetting operation of said CPU.

6. A data processing system according to claim 5,

wherein said AC signals on a plurality of said signal lines are AC signals of different frequencies or amplitudes.